JP4373770B2 - Optical disk device - Google Patents

Description

  The present invention relates to an optical disc apparatus for recording or reproducing digital data on an optical disc medium.

  As a recording medium capable of recording and reproducing digital data, an optical disk represented by a DVD can be mentioned. For example, a DVD-RAM, which is one of DVDs, includes a signal recording layer on a recording medium, and changes the crystal state of the recording layer by irradiating the signal recording layer with laser light having appropriate energy. When this recording layer is irradiated again with laser light of appropriate energy, an amount of reflected light corresponding to the crystalline state of the recording layer is obtained. By detecting this reflected light, digital data is recorded and reproduced.

Incidentally, in recent years, PRML technology has been adopted to increase the recording density (see Patent Document 1). This PRML technique is a system that combines the following partial response system and Viterbi decoding system (maximum likelihood decoding).
Partial response (PR) is a method of reproducing data while actively compressing intersymbol interference (interference between reproduced signals corresponding to adjacently recorded bits) and compressing a necessary signal band. . Depending on how the intersymbol interference is generated at this time, it can be further classified into a plurality of types of classes. Intersymbol interference is generated for the subsequent 1 bit.
The Viterbi decoding method (ML) is a kind of so-called maximum likelihood sequence estimation method, which effectively utilizes the intersymbol interference rules of the reproduction waveform and reproduces data based on signal amplitude information over a plurality of times. Do. For this processing, a synchronous clock synchronized with the reproduction waveform obtained from the recording medium is generated, and the reproduction waveform itself is sampled and converted into amplitude information by this clock. Thereafter, the waveform is converted into a response waveform of a predetermined partial response by performing appropriate waveform equalization, and the most probable data series is output as reproduction data using past and current sample data in the Viterbi decoding unit.
A method combining the above partial response method and Viterbi decoding method (maximum likelihood decoding) is the PRML method, and in order to apply this technology, an adaptive equalization technology that makes a reproduced signal a response of a target PR class, and The clock recovery technology that supports this is used.

  Next, the run length limit code used in the PRML technique will be described. The PRML reproducing circuit generates a clock synchronized with the signal itself reproduced from the recording medium. In order to generate a stable clock, it is necessary to reverse the polarity of the recording signal within a predetermined time. At the same time, in order to lower the maximum frequency of the recording signal, the polarity of the recording signal is not reversed during a predetermined time. Here, the maximum data length in which the polarity of the recording signal is not inverted is called the maximum run length, and the minimum data length in which the polarity is not inverted is called the minimum run length. A modulation rule with a maximum run length of 8 bits and a minimum run length of 2 bits is called (1,7) RLL, and a modulation rule with a maximum run length of 8 bits and a minimum run length of 3 bits is (2,7). 7) Call RLL. Typical modulation / demodulation methods used in optical disks include (1,7) RLL and EFM Plus (see Patent Document 2).

In an optical disk apparatus such as a DVD, a high-speed heading function for quickly starting reproduction of target data is required. Here, in general, since the linear velocity at the time of data recording / reproducing is made substantially constant in the optical disc apparatus, the rotational angular velocities on the inner circumference side and the outer circumference side of the recording medium are greatly different. Although there is a method in which the rotational angular velocity is always constant only during data reproduction, the reproduction signal frequency on the inner circumference side and the outer circumference side of the recording medium is greatly different because the linear velocity at the time of recording is constant. In order to realize high-speed heading in such a situation, high-speed optical head movement (high-speed seek) is performed, and even when the reproduction signal frequency is deviated from the original frequency (rotational angular velocity is deviated), the frequency / Phase synchronization needs to be established.
In the case of using the PRML technique, it is known that it is difficult to widen a capture range in which high-speed frequency / phase drawing can be performed in the timing recovery process (see Non-Patent Document 1).
JP-A-9-17130 US Pat. No. 5,696,505 Masaru Sawada, "A SIGNAL INTERPOLATED TIMING RECOVERY SYSTEM WITH FREQUENCY OFFSET DETECTOR", Digest of INTERMAG2003 DT-25, 2003.

In recent years, there has been proposed an optical disc apparatus that realizes a large capacity using a blue-violet laser. Furthermore, in addition to using a blue-violet laser with a short wavelength, it is conceivable to increase the linear recording density by adopting the above-mentioned PRML technology, and to further improve the data recording format to realize a large capacity.
In this case, it is a premise that the PRML technology is used, and in order to perform high-speed cueing, it is necessary to widen the capture range in the timing recovery.
Therefore, an object of the present invention is to provide an optical disc apparatus capable of phase synchronization based on a predetermined periodic signal (VFO region) included in a reproduction signal.

  In order to achieve the above object, the optical disc apparatus according to the present invention has a repetition period of at least twice the minimum run length d when the random data modulation rule is the minimum run length d and the maximum run length k. An optical disc apparatus for recording or generating an optical disc medium having an area in which repetitive data having a predetermined cycle less than twice k is recorded, a rotating mechanism for rotating the optical disc medium, and a light source for irradiating the optical disc medium with light A light receiving element that receives light emitted from the light source and reflected from the optical disk medium, a reference clock generation unit that generates a reference clock for recording or reproduction on the optical disk medium, and the light output from the light receiving element A phase control that controls the phase of the clock generated by the reference clock generation unit based on a signal corresponding to repeated data of a predetermined period. Characterized by comprising a part, the.

When an optical disc medium has a random data modulation rule having a minimum run length d and a maximum run length k, repetitive data having a predetermined cycle with a repetition cycle of not less than twice the minimum run length d and not more than twice the maximum run length k is recorded. Region (VFO region). Since repeated data of a predetermined period is recorded in this area, it can be used for phase control of a reference clock for reading information from the optical disk medium.
The frequency of the reference clock can be controlled based on this area. Alternatively, the frequency of the reference clock can be controlled using other means (for example, detection of a track wobble signal).

(1) Here, a signal generation unit that generates a signal corresponding to the repetition data of the predetermined period, a repetition signal of a predetermined period corresponding to the plurality of regions output from the light receiving element, and the signal generation unit And a phase error information generation unit that generates phase error information for controlling the phase of the reference clock generated by the reference clock generation unit based on the received signal.
Repetitive data of a predetermined period can be generated separately from signals from the light receiving element, and the phase of the clock can be controlled based on these signals to perform phase synchronization.

(2) The optical disc apparatus may further include an area detection unit that detects the area based on a signal output from the light receiving element.
Here, based on the correlation of the signal calculated by the correlation calculation unit, the correlation calculation unit that calculates the correlation between the signal output from the light receiving element and the signal before the predetermined clock of the signal. And a detection unit for detecting the region.
The presence of the area can be detected by utilizing the fact that what is recorded in the area is repeated data of a predetermined period. Specifically, by shifting the signal by the number of clocks corresponding to this predetermined period (for example, 4 clocks (1/2 period) when the period is 8 and 8 clocks (1 period)), the correlation is obtained, This region can be detected.

  (3) a first correlation calculator that calculates a correlation between a signal output from the light receiving element and a signal before the first predetermined clock of the signal; and a signal output from the light receiving element. Based on the calculation result of the second correlation calculation unit for calculating the correlation of the signal with the signal before the second predetermined clock different from the first predetermined clock, and based on the calculation result by the first and second correlation calculation units, the reference And a frequency control unit that controls a clock frequency of the clock generation unit.

  The clock frequency of the reference clock generator can be controlled by utilizing the fact that the data recorded in the area is repetitive data of a predetermined period. Specifically, if the correlation is made by shifting the signal by the number of clocks larger than the number of clocks corresponding to this predetermined period and the smaller number of clocks, it is determined whether the clock frequency used for signal reproduction is larger or smaller than the original frequency. Can be judged. Frequency synchronization can be performed by controlling the clock frequency based on the determination result.

  According to the present invention, it is possible to provide an optical disc apparatus capable of phase synchronization based on a predetermined periodic signal (VFO region) included in a reproduction signal.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
(Details of optical disk media)
A. Configuration of Optical Disc Medium First, details of the optical disc medium 100 according to the present invention will be described.
In the present embodiment, the data recorded on the optical disk medium 100 has a hierarchical structure of recording data as shown in FIG. 1 regardless of the type of the optical disk medium 100 (reproduction-only / addable / rewritable type). Yes.

That is, one ECC block 401, which is the largest data unit capable of detecting or correcting data errors, is composed of 32 sectors 230-241. Each sector 230 to 241 is composed of 26 sync frames (# 0) 420 to (# 25) 429. In one sync frame, a sync code 431 and sync data 432 are formed as shown in FIG. One sync frame includes 1116 (= 24 + 1092) channel bit data, and the sync frame length 433, which is a physical distance on the optical disc medium 100 on which the one sync frame is recorded, is almost constant everywhere ( (Excluding changes in physical distance for intra-zone synchronization).
An area in one ECC block (# 2) 412 composed of 32 sectors shown in FIG. 1 is called a data area 470.

B. FIG. 2 is a schematic diagram showing the first and second recording formats of the read-only optical disc medium 100. As shown in FIG.
FIG. 2A shows a first example, where the ECC blocks (# 1) 411 to (# 5) 415 are physically packed and continuously recorded on the optical disc medium 100. On the other hand, in the second example, as shown in FIG. 2B, guard areas (# 1) 441 to (# 8) 448 are inserted and arranged between the ECC blocks (# 1) 411 to (# 8) 418, respectively. Has been. The physical lengths of the guard areas (# 1) 441 to (# 8) 448 coincide with the sync frame length 433.

  FIG. 3 shows a detailed structure in the guard region in the second example shown in FIG. FIG. 1 shows that the structure in the sector is composed of the combination of the sync code 431 and the sync data 432. However, the guard area is also composed of the combination of the sync code 433 and the sync data 434, and the guard area (# 3) Modulated data is arranged in the sync data 434 area in 443 according to the same modulation rule as the sync data 432 in the sector.

  VFO (Variable Frequency Oscillator) areas 471 and 472 in FIG. 3 are used to synchronize the reference clock of the information reproducing apparatus or information recording / reproducing apparatus when reproducing the data area 470. As data contents recorded in the areas 471 and 472, data before modulation in a common modulation rule to be described later is “7Eh”, and the channel bit pattern actually recorded after modulation is “010001 000100”. The repeated pattern (a pattern in which “0” repeats three by three consecutively). In order to obtain this pattern, the first byte of the VFO areas 471 and 472 needs to be set to the state 2 in the modulation.

  The pre-sync areas 477 and 478 represent the boundary positions between the VFO areas 471 and 472 and the data area 470, and the recording channel bit pattern after modulation is a repetition of “100,000, 100,000” (a pattern in which “0” is repeated five times continuously). ing. The information reproducing apparatus or the information recording / reproducing apparatus detects the pattern change position of the repetitive pattern of “100,000,000,000” in the presync areas 477, 478 from the repetitive pattern of “010001,000100” in the VFO areas 471, 472, and the data area 470. Recognize that

The postamble area 481 indicates the end position of the data area 470 and the start position of the guard area 443.
The extra area 482 is an area used for copy control and unauthorized copy prevention. In particular, when not used for copy control or illegal copy prevention, all channel bits are set to “0”.
In the buffer area, the same data before modulation as in the VFO areas 471 and 472 is a continuous repetition of “7Eh”, and the channel bit pattern actually recorded after the modulation is a repetition pattern of “010001 000100” (three consecutive “0” s). Pattern). In order to obtain this pattern, the first byte of the VFO areas 471 and 472 needs to be set to the state 2 in the modulation.

  As shown in FIG. 3, the postamble area 481 in which the SY1 pattern is recorded corresponds to the sync code area 433, and the area immediately after the extra area 482 to the presync area 478 corresponds to the sync data area 434. In addition, an area from the VFO area 471 to the buffer area 475 (that is, an area including the data area 470 and a part of the guard area before and after the data area 470) is called a data segment 490 in the present embodiment, and is different from a physical segment described later. The contents are shown. Further, the data size of each data shown in FIG. 3 is expressed by the number of bytes of data before modulation.

C. Configuration of Optical Disc Medium in Recordable Type Address information recording format using wobble modulation in the recordable optical disc medium of the present embodiment will be described with reference to FIG.
In the address information setting method using wobble modulation, allocation is performed in units of the sync frame length 433 shown in FIG. Since one sector is composed of 26 sync frames, and one ECC block is composed of 32 sectors, one ECC block is composed of 26 × 32 = 832 sync frames.

Since the lengths of the guard areas 462 to 468 existing between the ECC blocks 411 to 418 coincide with one sync frame length 433, the length obtained by adding one guard area 462 and one ECC block 411 is 832 + 1 = 833. It is composed of sync frames. here,
833 = 7 × 17 × 7 (101)
Because it can be factored into a factor, it has a structural arrangement that takes advantage of this feature.
In other words, as shown in FIG. 4B, a data segment 531 is defined as a basic unit of rewritable data that is equal to the length of the area obtained by adding one guard area and one ECC block (as will be described later). The structure in the data segment in the rewritable optical disk medium and the recordable optical disk medium is exactly the same as the data segment structure in the read-only optical disk medium shown in FIG. Is divided into seven physical segments (# 0) 550 to (# 6) 556, and wobble address information 610 is stored for each physical segment (# 0) 550 to (# 6) 556. Record in advance in the form of wobble modulation.

As shown in FIG. 4, the boundary position of the data segment 531 and the boundary position of the physical segment 550 do not coincide with each other and are shifted by an amount described later. Further, each physical segment (# 0) 550 to (# 6) 556 is divided into 17 wobble data units (WDU: wobble data units) (# 0) 560 to (# 16) 576 (FIG. 4 ( c)). It can be seen from equation (101) that seven sync frames are allocated to the length of one wobble data unit (# 0) 560 to (# 16) 576.
Each wobble data unit (# 0) 560 to (# 16) 576 is composed of 16 wobble modulation areas and 68 wobble non-modulation areas 590 and 591. Since the groove or land is always wobbled at a constant frequency in the non-modulated areas 590 and 591, a PLL (Phase Locked Loop) is applied using the non-modulated areas 590 and 591 to record the recording marks recorded on the optical disk medium. It is possible to stably extract (generate) a reference clock for reproduction or a recording reference clock used for new recording.

By significantly increasing the occupation ratio of the non-modulation areas 590 and 591 to the modulation area, the accuracy and extraction (generation) stability of extraction (generation) of the reference clock for reproduction or extraction (generation) of the reference clock for recording are greatly increased. Can be improved. When moving from the non-modulation areas 590 and 591 to the modulation area, modulation start marks 581 and 582 are set using 4 wobbles, and wobble address areas 586 and 587 that are wobble modulated immediately after the detection of the modulation start marks 581 and 582 are performed. Arranged to come.
In order to actually extract the wobble address information 610, as shown in FIGS. 4D and 4E, the unmodulated areas 590 and 591 in the wobble segments (# 0) 550 to (# 6) 556 The wobble sync area 580 excluding the modulation start marks 581 and 582 and the wobble address areas 586 and 587 are collected and rearranged as shown in FIG. Here, since 180 degree phase modulation and NRZ (Non Return to Zero) method are employed, whether the wobble phase is 0 degree or 180 degrees and the address bit (address symbol) is "0" or "1"? Is set.

As shown in FIG. 4D, in the wobble address areas 586 and 587, 3 address bits are set in 12 wobbles. That is, one address bit is composed of four consecutive wobbles.
When the NRZ method is adopted, the phase does not change in four consecutive wobbles in the wobble address areas 586 and 587. The wobble pattern of the wobble sync area 580 and the modulation start marks 561 and 582 is set using this feature. That is, the wobble pattern that cannot be generated in the wobble address areas 586 and 587 is set for the wobble sync area 580 and the modulation start marks 561 and 582, thereby identifying the arrangement positions of the wobble sync area 580 and the modulation start marks 561 and 582. Making it easy.
In FIG. 4, the length of one address bit is set to a length other than four wobbles in the wobble sync area 580 relative to the wobble address areas 586 and 587 that constitute one address bit by four consecutive wobbles. That is, in the wobble sync area 580, the area where the wobble bit is “1” is set to 6 wobbles different from 4 wobbles and all the modulation areas (for 16 wobbles) in one wobble data unit (# 0) 560 are set. Is assigned to the wobble sync area 580, thereby improving the ease of detection of the start position of the wobble address information 610 (arrangement position of the wobble sync area 580).

The wobble address information 610 includes the following.
1. Track information 606, 607
This means the track number in the zone, and the address is determined on the groove (the indefinite bit is not included, so the indefinite bit is generated on the land) and the address is determined on the land (the indefinite bit is included). Since there is no land track information 607 (an indefinite bit is generated on the groove), it is recorded alternately. Also, track number information is recorded in a gray code or special track code only in the track information 606 and 607 portions.

2. Segment information 601
This is information indicating a segment number within a track (within one round in the optical disc medium 100). When the segment number is counted from “0” as the segment address information 601, a “000000” pattern in which 6 bits “0” continues in the segment address information 601 appears. In this case, it is difficult to detect the position of the boundary portion of the address bit area 511 (the black triangle mark portion), and a bit shift that detects the position of the boundary portion of the address bit area 511 is likely to occur. As a result, erroneous determination of wobble address information due to bit shift occurs. In order to avoid the above problem, in this embodiment, the segment number is counted from “000001”.

3. Zone identification information 602
A zone number in the optical disc medium 100 is indicated, and a value of “n” of Zone (n) is recorded.

4). Parity information 605
This is set for error detection during playback from wobble address information 610. 17 address bits from segment information 601 to reservation information 604 are individually added. If the addition result is an even number, "0" is set to an odd number. In this case, “1” is set.

6). Unity area 608
As described above, each wobble data unit (# 0) 560 to (# 16) 576 is set so as to be composed of a modulation area for 16 wobbles and non-modulation areas 590 and 591 for 68 wobbles. The occupation ratio of the non-modulation regions 590 and 591 is greatly increased. Further, the occupation ratio of the non-modulation areas 590 and 591 is expanded to further improve the accuracy and stability of extraction (generation) of the reproduction reference clock or recording reference clock. The location where the unity area 608 shown in FIG. 4E is included is in the wobble data unit (# 16) 576 in FIG. 4C and in the wobble data unit (# 15) immediately before that, although not shown. This is exactly the case. In the monotone information 608, all six address bits are “0”. Therefore, modulation start marks 581 and 582 are not set in the wobble data unit (# 16) 576 including the monotone information 608 and the wobble data unit (# 15) immediately before the wobble data unit (# 16) 576. It is a phase-unmodulated region.

The data structure shown in FIG. 4 will be described in detail below.
The data segment 531 includes a data area 525 in which 77376 bytes of data can be recorded. The length of the data segment 531 is usually 77469 bytes, and the data segment 531 has a 67-byte VFO area 522, a 4-byte presync area 523, a 77376-byte data area 525, a 2-byte postamble area 526, and a 4-byte extra. An area (reserved area) 524 is composed of a buffer area field 527 of 16 bytes. The layout of the data segment 531 is shown in FIG.

The data in the VFO area 522 is set to “7Eh”. The modulation state is set to State 2 in the first byte of the VFO area 522. The modulation pattern of the VFO region 522 is a repetition of the pattern “010001 000100”.
The postamble area 526 is recorded with the sync code SY1.
The extra area 524 is reserved, and all bits are set to “0b”.
The data in the buffer area 527 is set to “7Eh”. The state of modulation of the first byte of the buffer area 527 depends on the last byte of the reserved area. The modulation pattern of the buffer area other than the first byte is the pattern “010001 000100”.

  Data to be recorded in the data area 525 is called a data frame, a scrambled frame, a recording frame, or a physical sector depending on the stage of signal processing. The data frame includes 2048-byte main data, 4-byte data ID, 2-byte ID error detection code (IED), 6-byte reserved data, and 4-byte error detection code (EDC). After the EDC scrambled data is added to the 2048-byte main data in the data frame, a scrambled frame is formed. A Cross Reed-Solomon error correction code is provided over the 32 scrambled frames of the ECC block.

The recording frame is scrambled by adding an outer code (PO) and an inner code (PI) after ECC encoding. PO and PI are generated for each ECC block composed of 32 scrambled frames.
After ETM processing for adding a sync code to the head of a recording frame for every 91 bytes, the recording data area is made a recording frame. 32 physical sectors are recorded in one data area.
NPW and IPW are recorded on the track. The NPW starts to fluctuate toward the outside of the disk, and the IPW starts to fluctuate toward the inside of the disk. The start point of the physical segment is equal to the start point of the sync area.
The physical segment is aligned with wobble addressed periodic wobble address position information (WAP). Each WAP information is indicated by 17 wobble data units (WDU). The length of the physical segment is equal to 17 WDU.

D. Configuration of Rewritable Optical Disk Medium FIG. 5 shows a recording format of rewritable data recorded on the rewritable optical disk medium. In the present embodiment, rewriting of rewritable data is performed in units of recording clusters 540 and 541 shown in FIGS. 5B and 5E. As will be described later, one recording cluster includes one or more data segments 529 to 531 and an extended guard area 528 arranged last. That is, the start of one recording cluster 531 coincides with the start position of the data segment 531 and starts from the VFO area 522.
When a plurality of data segments 529 and 530 are continuously recorded, a plurality of data segments 529 and 530 are continuously arranged in the same recording cluster 531 as shown in FIGS. At the same time, since the buffer area 547 existing at the end of the data segment 529 and the VFO area 532 existing at the beginning of the next data segment are continuously connected, the phase of the recording reference clock at the time of recording between them is Match. When the continuous recording is finished, the extended guard area 528 is arranged at the last position of the recording cluster 540. The data size of the extended guard area 528 has a size of 24 data bytes as data before modulation.

  As can be seen from the correspondence between FIGS. 5A and 5C, the rewritable guard areas 461 and 462 include the postamble areas 546 and 536, the extra areas 544 and 534, the buffer areas 547 and 537, and the VFO areas 532 and 522, respectively. The pre-sync areas 533 and 523 are included, and the extended guard area 528 is disposed only at the continuous recording end location.

  As shown in FIG. 6, the next overlapping portion of the VFO area 522 and the extended guard area 528 comes after 24 wobbles from the start position of the physical segment, but as shown in FIG. 4D, 16 wobbles from the start of the physical segment 550 are obtained. Up to this time, the wobble sync area 580 is obtained, but 68 wobbles thereafter become the unmodulated area 590. Therefore, the portion where the next VFO region 522 and the extended guard region 528 after 24 wobbles overlap is in the non-modulation region 590.

The recording film in the rewritable optical disk medium in the present embodiment uses a phase change recording film. In the phase change recording film, the deterioration of the recording film starts near the rewrite start / end position. Therefore, if the recording start / recording end at the same position is repeated, the number of rewrites is limited due to the deterioration of the recording film. In this embodiment, in order to alleviate the above problem, at the time of rewriting, the recording start position is shifted at random by shifting by Jm + 1/12 data bytes as shown in FIG.
4C and 4D, for explaining the basic concept, the head position of the extended guard area 528 coincides with the head position of the VFO area 522, but strictly speaking, the VFO area 522 as shown in FIG. The head position of is shifted randomly.

  In FIG. 5E, it is necessary to set the recording start position of the recording cluster 541 accurately. In the information recording / reproducing apparatus of the present embodiment, the recording start position is detected using a wobble signal recorded in advance on a rewritable or write once optical disc medium. As can be seen from FIG. 4D, the pattern changes from NPW to IPW in units of 4 wobbles except for the wobble sync area 580. In contrast, in the wobble sync area 580, the wobble switching unit is partially shifted from 4 wobbles, so that the wobble sync area 580 is most easily detected. Therefore, in the information recording / reproducing apparatus according to the present embodiment, after the position of the wobble sync area 580 is detected, the recording process is prepared and recording is started. Therefore, the start position of the recording cluster 541 needs to be in the unmodulated area 590 immediately after the wobble sync area 580.

  FIG. 6 shows the contents. A wobble sync area 580 is arranged immediately after the physical segment is switched. As shown in FIG. 4D, the length of the wobble sync area 580 is 16 wobble cycles. Further, after detecting the wobble sync area 580, 8 wobble cycles are required in preparation for recording processing in anticipation of a margin. Therefore, as shown in FIG. 6, the head position of the VFO area 522 existing at the head position of the recording cluster 541 needs to be arranged at least 24 wobbles behind the physical segment switching position in consideration of the random shift.

  As shown in FIG. 5, the recording process is performed many times in the overlapping portion 541 at the time of rewriting. When rewriting is repeated, the physical shape of the wobble groove or wobble land changes (deteriorates), and the wobble reproduction signal quality from there changes. In this embodiment, as shown in FIG. 5 (f) or FIGS. 4 (a) and 4 (d), it is avoided that the overlapping portion 541 at the time of rewriting is in the wobble sync area 580 or the wobble address area 586, and no modulation is performed. It is devised to record in the area 590. In the non-modulation area 590, only a constant wobble pattern (NPW) is repeated. Therefore, even if the wobble reproduction signal quality partially deteriorates, it can be interpolated using the preceding and following wobble reproduction signals.

(Configuration of recording / reproducing circuit)
FIG. 7 is a diagram showing a configuration of a recording / reproducing circuit corresponding to the rewritable medium according to the first embodiment of the present invention.
The modulation circuit 115 converts the recording data into modulation data according to a predetermined rule such as a run length limit code. The obtained modulated data is finely adjusted by the recording compensation control circuit 114 so that the pulse width can be correctly recorded on the recording medium.
The optical disc medium 100 records or reproduces data by irradiating an appropriate laser beam from the optical head 101.
At the time of data recording, the optical head 101 receives a recording pulse signal subjected to appropriate recording compensation by the recording compensation control circuit 114, and irradiates the optical disc medium 100 with an appropriate laser beam corresponding to the recording data. Further, at the time of data reproduction, the optical head 101 irradiates a laser beam with appropriate power and detects reflected light from the optical disc medium 100, so that a difference signal 103 including address information and a sum signal 102 including data information are displayed. Two types of signals are output.

  These two signals will be described with reference to FIG. FIG. 8 shows the relationship between the track on the recording medium and the laser beam spot. As described above, the recording track on the rewritable medium slightly wobbles in the radial direction. The reflected light is detected by the sensor of the optical head 101, and the optical sensor is divided in the radial direction as shown in FIG. The signals detected by the sensors are connected as shown in FIG. Here, since the sum signal 102 side has a signal level corresponding to the track width in the beam spot, a signal corresponding to the crystal state of the optical disc medium 100 is obtained, whereas the difference signal 103 is a meandering track. A signal corresponding to (wobbling) is obtained.

  The sum signal 102 output from the optical head 101 of FIG. 7 becomes an input signal of the analog / digital converter 106 through the high-pass filter 104 and the low-pass filter 105. The sum signal 102 includes a direct-current component in the signal in principle of the optical head 101, but a high-pass filter 104 having a cutoff frequency of about 1 kHz is used to facilitate subsequent processing. Further, a low-pass filter 105 is used for band limiting (anti-aliasing) processing for performing analog-digital conversion. The output signal of the low-pass filter 105 is converted into a digital signal by the analog / digital converter 106. The frequency / phase control circuit 108 performs control so that the conversion timing at this time is appropriate. Waveform equalization is performed in the adaptive equalizer 107 so that the output signal of the analog / digital converter 106 has a response of a predetermined PR class, typically PR (3443). The adaptive learning circuit 109 performs adjustment so that the equalization characteristics at this time are appropriate. The specific configurations of the adaptive equalizer 107 and the adaptive learning circuit 109 are disclosed in Japanese Patent Laid-Open No. 2001-344903 and many other documents, and will be further described later.

  The output of the adaptive equalizer 107 is waveform-equalized into a predetermined PR class, and the Viterbi decoder 110 performs maximum likelihood sequence estimation (Viterbi decoding) to obtain binary data. Here, the recording data sequence is recorded as data of every 1116 bits called a frame, but a 24-bit binary data sequence (SYNC code) representing the start position of each frame is detected, and every 12 bits for demodulation processing in the subsequent stage. The SYNC detection / synchronization circuit 111 generates the synchronization signal. The demodulating circuit 112 demodulates the 12-bit binary data output from the SYNC detection / synchronizing circuit 111 into 8-bit reproduction data according to a predetermined rule.

  Next, adaptive learning in the adaptive equalizer 107 and the adaptive learning circuit 109 will be described with reference to FIG. This figure is a block diagram showing details of the adaptive equalizer 107 and the adaptive learning circuit 109. In this figure, reference numerals 201 and 202 denote delay circuits which output an input signal with a delay of one clock. Reference numerals 203, 204, and 205 denote multiplication circuits that output the product of two input values. Reference numerals 206, 207, and 208 denote addition circuits that output the sum of two input values. Although FIG. 9 shows an example of a 3-tap digital filter using three multipliers, the basic operation is the same even if the number of multipliers changes, and only the case of 3-tap will be described.

Assuming that the input signal of the adaptive equalizer 107 at time k is x (k) and the multipliers input to the multipliers 203, 204, 205 are c1, c2, c3, respectively, the output Y ( k) can be expressed by the following equation.
Y (k) = x (k) * c1 + x (k-1) * c2 + x (k-2) * c3 (1)
Let A (k) be binary data obtained by the Viterbi decoder 110 for Y (k). If the target PR class is, for example, PR (3 4 4 3) and A (k) is correct reproduction data, the original output Z (k) of the adaptive equalizer 107 at time k is It becomes the following formula.
Z (k) = 3 * A (k) + 4 * A (k-1) + 4 * A (k-2) + 3 * A (k-3) -7 (2)
Therefore, the equalization error E (k) at time k is defined by the following equation.
E (k) = Y (k)-Z (k) (3)

In adaptive learning, the coefficient of each multiplier is updated according to the following equation.
c1 (k + 1) = c1 (k) -α * x (k) * E (k) (4)
c2 (k + 1) = c2 (k) -α * x (k-1) * E (k) (5)
c3 (k + 1) = c3 (k) -α * x (k-2) * E (k) (6)
Α in the equations (4) to (6) is an update coefficient, and a small positive value (for example, 0.01) is set.

  The waveform synthesis circuit 216 performs the processing shown in the above equation (2). The delay circuit 215 delays the output Y (k) of the adder circuit 208 corresponding to the processing time in the Viterbi decoder 110, and the adder circuit 217 performs the process shown in the above equation (3). The coefficient update circuit 212 updates the coefficient of the multiplier 203 by performing the calculation shown in Equation (4). The update result is stored in the register 209. The coefficient update circuit 213 updates the coefficient of the multiplier 204 by performing the calculation shown in the equation (5). The update result is stored in the register 210. The coefficient update circuit 214 updates the coefficient of the multiplier 205 by performing the calculation shown in Equation (6). The update result is stored in the register 211. As described above, adaptive learning of the adaptive equalizer 107 is performed.

Next, details of the address reproducing circuit will be described with reference to FIG. Here, it is assumed that the address information is expressed by modulating the difference signal (wobble signal).
FIG. 10 shows an example of an address reproduction circuit for obtaining address information from a phase-modulated difference signal (wobble signal).

  The wobble signal includes noise peculiar to the medium and noise caused by crosstalk from adjacent tracks. For this reason, it is necessary to remove noise other than the frequency band of the wobble signal through a bandpass filter (BPF) or the like. The noise-removed wobble signal is input to a phase detector and a phase-locked loop circuit (PLL) to generate a carrier wave.

The PLL performs phase synchronization processing and outputs a carrier wave synchronized with the wobble signal. In the phase detector, phase detection processing is performed by a wobble signal and a carrier wave synchronized with the wobble signal. As a typical method of the phase detection process, there is a method of determining the phase polarity by multiplying a modulation signal and a carrier wave. The multiplied waveform is detected in a form offset by the first phase and the second phase.
Thereafter, the high frequency (double frequency of the original waveform) generated by the phase detection is removed using a low pass filter (LPF) or the like. The signal is binarized by detecting the threshold value of the waveform after LPF with a slicer.

  In order to obtain bit information of an address from a binarized waveform, a clock (hereinafter referred to as symbol clock) synchronized with the address bit is required. The symbol clock is generated using a wobble clock synchronized with the wobble cycle output from the PLL and a binarized signal output from the slicer. The symbol clock generator performs processing so that the waveform obtained by dividing the wobble clock by 1 / N is synchronized with the binarized signal.

  Here, N is determined by the wobble wave number used to express one address bit. For example, when one address bit is composed of four wobble waves, the polarity of the binarized signal is switched by the number of wobble waves that is a multiple of four. The shortest modulation period at this time is 4 wobbles. That is, if N is set to 4, a clock synchronized with the address bits can be generated.

  The 1 / N divided wobble clock synchronized with the binarized signal is sent to the address decoder as a symbol clock. The address decoder decodes the address using the binary signal and the symbol clock input from the slicer. However, the wobble is generally modulated to include not only the physical address information but also a synchronization signal indicating the start position of the address information.

  The synchronization signal is often modulated with a modulation period different from that of the address bit in order to prevent misidentification with the address information. In this case, the symbol clock needs to be generated with the minimum modulation period including the synchronization signal. However, when the synchronization signal is detected by a method different from the address bit detection (for example, detection in units of one wobble wave), the symbol clock may be matched with the shortest modulation period of the address bits.

  As described above, address information can be obtained from the modulated wobble signal. Further, since the difference signal and the sum signal have the positional (time) relationship shown in FIG. 5 and FIG. 6 described above, the next signal after 24 wobble cycles from the last point of the seventh wobble segment of each ECC block. It is clear that the ECC block data begins. A predetermined periodic signal (VFO area) is recorded at the head of each ECC block. In this region, since a reproduction signal having a single period can be obtained, it is possible to realize phase pull-in that maintains a wide capture range.

  The frequency / phase pull-in in this embodiment is performed by the following three steps. As a first step, a frequency pull-in operation utilizing the fact that the period of the difference (wobble) signal is 93 times the channel clock period. As a second step, a VFO pattern phase pull-in step that can operate only in the VFO region. The third step is the above-described three-stage operation, which is the tracking phase pull-in that can operate even in a random data region.

Next, the frequency / phase acquisition sequence according to the present invention will be described in detail with reference to the drawings. FIG. 11 is a diagram showing details of the frequency / phase control circuit 108.
The frequency / phase control circuit 108 includes a tracking phase comparator 120, a VFO pattern phase comparator 121, a frequency comparator 122, a changeover switch 123, a loop filter 124, a digital / analog converter 125, and a voltage controlled oscillator 126. Consists of elements.

The function of each component shown in FIG. 11 will be briefly described.
The follow-up phase comparator 120 compares the phase of the reproduced signal with respect to random data whose recording data is unknown, and outputs a value corresponding to the phase error of the sample timing in the analog / digital converter 106.
The VFO pattern phase comparator 121 outputs a value corresponding to the phase error of the sample timing in the analog / digital converter 106 in the same manner as the follow-up phase comparator 120, but only during reproduction of a VFO area in which recorded data is known. It is a phase comparator that functions effectively.

The frequency comparator 122 detects a value corresponding to the sampling frequency error in the analog-to-digital converter 106.
The changeover switch 123 appropriately switches the connection between the follow-up phase comparator 120, the VFO pattern phase comparator 121, the frequency comparator 122, and the loop filter 124 so that the frequency / phase can be pulled in by an appropriate sequence. .

The loop filter 124 forms a second-order PLL loop by performing appropriate calculations on the phase error signal and the frequency control signal from the follow-up phase comparator 120, the VFO pattern phase comparator 121, and the frequency comparator 122. A signal for driving the controlled oscillator 126 is generated.
The digital / analog converter 125 converts the digital signal output from the loop filter 124 into an analog signal.

  The voltage controlled oscillator 126 generates a clock having a frequency corresponding to the voltage output from the digital / analog converter 125. In the example of FIG. 11, it is assumed that the voltage output from the digital-analog converter 125 and the oscillation frequency of the voltage controlled oscillator 126 are in an inversely proportional relationship.

Hereinafter, the operation according to each step will be described.
In the first step, the frequency control is performed so that the oscillation frequency of the voltage controlled oscillator 126 is substantially equal to the channel clock frequency. As described above, since the period of the wobble clock output from the address generation circuit is 93 times the channel clock period, the frequency comparator 122 in FIG. 11 counts the period of the wobble clock with the clock of the voltage controlled oscillator 126.

  The counter 129 in FIG. 11 is a counter that counts up according to the output of the voltage controlled oscillator 126. The counter 129 resets the count value to zero at the rising edge of the wobble clock. At the same time, the count value before reset is taken into the flip-flop 130.

When the captured period is smaller than 93, the difference is multiplied by an appropriate gain G3, and this is output to the loop filter, thereby raising the oscillation frequency of the voltage controlled oscillator 126. If the obtained period is greater than 93, the difference is multiplied by an appropriate gain G3 and output to the loop filter to lower the oscillation frequency of the voltage controlled oscillator 126. At this time, the selector switch 123 is connected so that the frequency comparator 122 becomes effective.
In this way, the oscillation frequency of the voltage controlled oscillator 126 can be made approximately equal to the channel rate of the reproduction signal.

  In the second step, the VFO pattern phase comparator 121 performs a wide capture frequency / phase pull-in using a reproduction signal in the VFO region. As described above, when the last time point of the seventh segment of each ECC block is detected by the wobble address reproduction circuit, the reproduction signal of the VFO area is started as a sum signal after 24 wobble cycles. Therefore, the VFO pattern phase comparator 121 is enabled by switching the changeover switch 123 after a predetermined time has elapsed since the last time point of the seventh segment of each ECC block has been detected.

  In the case of the present embodiment, the recording signal in the VFO area is a single-cycle signal in which one cycle is 8 channel bits. Here, if the PR class is (3443), the equalized output is (..0, 4, 7, 4, 0, -4, -7, -4, 0, 4, 7, ..) .

FIG. 12 is a diagram showing details of the VFO pattern phase comparator 121. The VFO pattern phase comparator 121 is mainly composed of a zero phase detector and a phase comparator.
The zero phase detector selects one of the eight possible reproduction signal patterns in the VFO area, that is, one of the patterns 00001111, 00011110, 00111100, 01111000, 11110000, 11100001, 11000011, and 10000111, and In order to use this pattern as a reference for phase comparison, this pattern is self-generated.

In order to perform such an operation, first, the switch 151 is connected to the upper side when the operation of the VFO pattern phase comparator 121 is started. The sign determination unit 150 compares the current input signal Y (k) with the input Y (k-3) three times before. If the value of the current input Y (k) is greater than Y (k-3), "1" is output, otherwise "0" is output. The output of the sign determination unit 150 is sequentially transmitted to the flip-flops 152, 153, 155, and 156 and the inversion circuit 154 as shown in FIG.
When a predetermined time (for example, 8 clocks) elapses after the operation of the VFO pattern phase comparator 121 starts, the switch 151 is connected to the lower side. Then, the flip-flops 152 and 153, the inverting circuit 154, and the flip-flops 155 and 156 form an oscillation loop that generates a VFO pattern as a reference for phase comparison. The output of the flip-flop 155 propagates to the flip-flops 157, 158, and 159 with a one-time delay.
Here, the output of the flip-flop 155 is A (k), the output of the flip-flop 157 is A (k-1), the output of the flip-flop 158 is A (k-2), and the output of the flip-flop 159 is A (k- 3). The pattern determination circuit uses the outputs of the flip-flops 155, 157, 158, and 159 to determine which phase of the current equalization output signal is close to the predetermined periodic signal in the VFO region.

In combination with the above processing, the equalized output Y (k) is sequentially delayed by the flip-flops 160, 161, 162, and 163 one hour at a time. The output of the flip-flop 161 is Y (k-2), and the output of the flip-flop 163 is Y (k-4). A phase error PD is output from the equalized output according to the following equation.
When A (k), A (k-1), A (k-2), A (k-3) = [1111], PD = 0
When A (k), A (k-1), A (k-2), A (k-3) = [1110], PD = Y (k) -Y (k-2)
When A (k), A (k-1), A (k-2), A (k-3) = [1100], PD = Y (k) -Y (k-4)
When A (k), A (k-1), A (k-2), A (k-3) = [1000], PD = Y (k) + Y (k-2)
When A (k), A (k-1), A (k-2), A (k-3) = [0000], PD = 0
When A (k), A (k-1), A (k-2), A (k-3) = [0001], PD = -Y (k) + Y (k-2)
When A (k), A (k-1), A (k-2), A (k-3) = [0011], PD = -Y (k) + Y (k-4)
When A (k), A (k-1), A (k-2), A (k-3) = [0111], PD = -Y (k) -Y (k-2) (7)

The selection circuit 164 selects the phase error according to the output of the pattern determination circuit 165. Such a phase comparison operation is premised on the fact that the recording pattern of the VFO area is known, and since the phase comparison frequency is high, a wide capture range can be achieved.
The equation (7) shown here is determined by the relationship between the recording signal cycle in the VFO area and the PR class to be used. Even when other periods or other PR classes are used, the present invention can be easily applied.

The third step is a phase comparison for follow-up operation that operates even in a non-VFO region (random region) before the end of the VFO region. In the second step, it is assumed that the recording pattern is known, but in the third step, phase comparison is possible even for an unknown recording pattern. After the start of the phase comparison operation in the second step, the connection of the changeover switch 123 is changed after a predetermined time and the process proceeds to the third step. The tracking phase comparator 120 in FIG. 11 is used at this time. Here, the phase error PD is output according to the following equation.
If Y (k)> 0 and Y (k-1) <= 0, PD =-(Y (k) + Y (k-1))
If Y (k) <= 0 and Y (k-1)> 0, PD = + (Y (k) + Y (k-1))
Other than above PD = 0 (8)

  By performing the phase comparison according to the above equation (8), the phase comparison can be performed even for an unknown recording pattern. In both steps 2 and 3, the loop filter 124 performs an appropriate calculation on the obtained phase error signal. The output of the loop filter 124 is converted into an analog signal by the digital / analog converter 125 and then the oscillation frequency of the voltage controlled oscillator 126 is controlled. As described above, the arrival of the VFO area in the rewritable medium is detected, and the timing recovery of the high-speed and wide capture range can be realized by using the signal in this area.

(Second Embodiment)
Next, a second embodiment of the present invention using a read-only medium will be described.
In the case of a read-only medium, unlike a rewritable medium, there is no wobble signal. Therefore, since the address reproduction circuit does not function, the arrival of the VFO area cannot be known in advance.
However, since there is no overwriting operation of recorded data in a read-only medium, it is guaranteed that the entire VFO area in FIGS. 2 and 3 is a continuous single period signal, and at the same time, it is effective because no overwriting operation occurs. There is a feature that the length (time) of the usable VFO area is longer than that of the rewritable medium.
Therefore, in the second embodiment, the arrival of the VFO area is self-detected in the first half of the VFO area, and the recording pattern of the VFO area is known in the second half of the VFO area as in the first embodiment. Use the phase pull-in. That is, frequency / phase pull-in in the read-only medium is performed according to the following steps.

First, as a first step, the VFO area is detected in an asynchronous state. As a second step, VFO pattern phase pull-in that can operate only in the VFO region is performed. As a third operation, tracking phase pull-in that can operate even in a random data region is performed. The above three-stage operation.
Among these, the second and third steps are the same operations as in the first embodiment.
FIG. 13 is a diagram showing a configuration of a reproduction circuit corresponding to a reproduction-only medium according to the present invention. The difference between FIG. 13 and FIG. 7 is that the address reproduction circuit 113 does not exist in FIG. 13 and the VFO area detection circuit 116 exists.

Next, details of the VFO region detection circuit 116 will be described with reference to the block diagram of FIG. The VFO region detection circuit 116 includes a correlation calculation unit, an averaging unit, and a detection unit.
The correlation calculation unit detects a predetermined periodic pattern specific to the VFO region by calculating the autocorrelation of the input signal. Specifically, the input signal is Y (k), and this signal is delayed by the flip-flops 170, 171, 172, and 173 respectively by one time. Then, the output of the flip-flop 173 becomes Y (k−4) which is delayed by 4 times with respect to the input signal Y (k).

  In the multiplication circuit 174, Y (k) * Y (k-4) is calculated. As described above, in the VFO area, a signal having a constant period of 8 channel clock is recorded. Therefore, in the signal in the VFO region, the autocorrelation that is four times away is just a reverse-phase relationship, and the negative correlation is maximum. Even if the oscillation frequency of the voltage controlled oscillator 126 slightly deviates from the channel clock frequency of the reproduction signal, a negative correlation with a strong autocorrelation that is four hours away in the VFO region is expressed.

  However, since an actual reproduction signal includes various noise components, the averaging unit performs an averaging process for removing the noise components. In the example of FIG. 14, if the output of the correlation calculation unit is Z (k), the sum of the values of Z (k) of four consecutive samples, that is, Z (k) + Z (k-1) + Z (k- 2) Calculate + Z (k-3). The four samples in the total section may be set to appropriate values depending on the signal-to-noise ratio of the actual reproduction signal, and the same effect can be obtained with six or eight samples. The output value of the averaging unit is evaluated for the strength of negative correlation in the detection unit.

The counter 180 is a counter that increments by 1 when the input is “1” and resets the output to 0 when the input is “0”. That is, when the output value of the averaging unit is a negative value, the counter 180 counts up, and when the output value of the averaging unit is a positive value, the counter 180 is reset to 0. The output of the counter 180 is compared with a predetermined threshold value (VFth), and when the value of the counter 180 is larger than the threshold value (VFth), the VFO area detection output becomes “1”.
With this configuration, the VFO area detection output becomes “1” about VFth + α bits after the start of reproduction of the VFO area, and the VFO area detection output becomes “0” almost simultaneously with the end of the VFO area. As described above, the arrival of the VFO area can be detected even in the asynchronous state.
After detecting the VFO region, the phase capture operation of the second step in the first embodiment is started, so that wide capture frequency / phase capture can be realized as in the case of the rewritable medium. .

(Third embodiment)
Next, a third embodiment that further improves the second embodiment will be described.
As described above, since there is no wobble signal in the read-only medium, frequency comparison using the wobble signal in the first embodiment cannot be performed. In order to solve this problem, a function of performing frequency comparison using a reproduction signal in the VFO region is added to the second embodiment.

  FIG. 15 is a diagram illustrating a configuration of a VFO region detector including a frequency comparison function according to the third embodiment. The function shown in FIG. 15 corresponds to the VFO region detection circuit 116 shown in FIG. 14 added with a function similar to the frequency comparator of FIG. Among these, the configuration and operation of the VFO region detection unit are the same as those described in the second embodiment, and thus the description thereof is omitted here.

  The frequency comparison unit in the third embodiment includes two different VFO region detection units. One is a VFO area detector for detecting a single period signal with a period of 6 samples, and the other is a VFO area detector for detecting a period signal with a period of 10 samples. . For convenience of explanation, the former is called a 6T pattern detector, the latter is called a 10T pattern detector, and the VFO region detector shown in FIG. 14 is called an 8T pattern detector. These differences in configuration are as follows. In each correlation calculation unit, the 6T pattern detection unit calculates the correlation with the signal delayed by 3 times, the 8T pattern detection unit calculates the correlation with the signal delayed by 4 times, and 10T The pattern detection unit calculates the correlation with the signal delayed by 5 times.

  When the oscillation frequency of the voltage controlled oscillator 126 is much higher than the actual channel rate, the reproduction signal in the VFO region whose original period is 8 samples is erroneously detected as if it is a signal with a longer period. Then, only the 10T pattern detection unit outputs “1”. In this case, control is performed with an appropriate gain G3 so as to lower the oscillation frequency of the voltage controlled oscillator 126. On the contrary, when the oscillation frequency of the voltage controlled oscillator 126 is much lower than the actual channel rate, the reproduction signal in the VFO region whose original period is 8 samples is erroneously detected as if it is a signal with a shorter period. . Then, only the 6T pattern detection unit outputs “1”. In this case, control is performed with an appropriate gain G3 so as to increase the oscillation frequency of the voltage controlled oscillator 126. When the oscillation frequency of the voltage controlled oscillator 126 approaches the actual channel rate, the VFO region detection signal becomes “1” as described in the second embodiment. After that, the phase pull-in operation is started as shown in the second embodiment. As described above, the frequency pull-in operation can be performed also in the read-only medium.

(Fourth embodiment)
Next, a fourth embodiment in which the adaptive learning function is controlled by detecting the arrival of the VFO region in the first, second, or third embodiment will be described. In order for the adaptive learning function of the adaptive equalization circuit and the adaptive learning circuit shown in FIG. 9 to function correctly, the channel clock establishes phase synchronization, and the analog / digital converter 106 performs analog / digital conversion at the correct timing. It needs to be done. Further, in order to read the recorded data correctly, it is necessary to adjust the equalization characteristic to an optimum state using the adaptive learning function. However, it is difficult to detect by itself that the channel clock has established phase synchronization with a low signal-to-noise ratio of the reproduced signal. However, the phase acquisition sequence according to the invention can establish phase synchronization upon completion of the second step with very high probability.

Therefore, in the first, second, or third embodiment, the adaptive learning function is enabled when a predetermined minimum time has elapsed after the start of the third step of the phase acquisition sequence. Specifically, the following sequence is performed.
In the first, second, or third embodiment, in the first and second steps of phase pull-in, the equalization coefficients c1, c2, and c3 in FIG. The coefficient obtained in advance is set so as to be close to. At the same time, α in equations (4), (5), and (6) is set to zero. Adaptive learning does not work by setting α to zero. In this state, phase drawing is performed according to the procedure described in the first, second, or third embodiment. When a predetermined minimum time has elapsed since the start of the third step of phase pull-in, α in equations (4), (5), and (6) is set to an appropriate value greater than zero. Then, appropriate feedback is applied to the equalization coefficients c1, c2, and c3, and adaptive learning functions. As described above, the adaptive learning function can be started quickly.

(Fifth embodiment)
Next, in the first, second, third, and fourth embodiments, an embodiment for speeding up the operation of the SYNC detection / synchronization circuit 111 will be described. First, for easy understanding, a frame structure of a recording data string will be briefly described with reference to FIG. Data recorded on the medium is divided into data of every 2 KB called a sector. One sector is further divided into data called 26 frames. One frame is composed of a total of 1116 bits including a 24-bit binary data sequence (SYNC code) representing the start position of the frame and 1092 bits of modulated recording data. There are four types of SYNC codes: SY0, SY1, SY2, and SY3. This is called the SYNC number. SYNC codes are inserted in the order shown in FIG. 16 at the head of each frame in the sector. That is, SY0 at the beginning of the first frame, SY1 at the beginning of the second frame, SY1 at the beginning of the third frame, SY1, SY2, SY1, SY1, SY3, SY1, SY2, SY2, SY1 , SY3, SY2, SY1, SY2, SY3, SY3, SY3, SY2, SY2, SY2, SY3, SY2, SY3, SY1 are inserted in this order.

  For convenience of explanation, the frames in each sector are called the 0th frame, the first frame, the second frame,..., The 25th frame in order from the top, and this number is called the frame number. The frame structure in the sector shown in FIG. 16 is characterized in that the frame number can be obtained from three or more consecutive SYNC numbers. Here, in order to perform the error correction process, which is a process subsequent to the configuration shown in FIG. 1, the frame number of the reproduced data is required. Therefore, after detecting the SYNC number of at least three consecutive frames. Otherwise, error correction processing cannot be performed.

  As described above, the SYNC detection / synchronization circuit 111 detects a 24-bit binary data string (SYNC code) representing the start position of each frame, and generates a 12-bit synchronization signal for demodulation processing in the subsequent stage. As a configuration example of the SYNC detection / synchronization circuit 111, details thereof are disclosed in, for example, Japanese Patent Application Laid-Open No. 5-292055.

FIG. 17 is a block diagram showing the configuration of the SYNC detection / synchronization circuit 111.
In this figure, the reproduction data is a 1-bit binary data string output from the Viterbi decoder 110 of FIG. 7 or FIG.
The channel clock is a clock generated by the voltage controlled oscillator 126.
The SYNC detection circuit 301 determines whether or not the reproduction data string matches the SYNC code. If they match, the SYNC detection pulse is generated and the detected SYNC number is output at the same time. In the generated SYNC detection pulse, the synchronization protection circuit 302 removes the SYNC detection pulse detected in error. When the SYNC detection pulse generated by the SYNC detection circuit 301 is a correct detection pulse, it becomes an output pulse of the synchronization protection circuit 302 as it is.

  The frame counter 303 is a circuit that counts up an internal counter every time a channel clock is input. At the same time, when there is a pulse input from the synchronization protection circuit 302, the frame counter 303 resets the counter value to zero. As described above, the SYNC code is inserted every 1116 bits. Therefore, when the count value of the frame counter 303 is close to 1116, the synchronization window signal is activated. The synchronization protection circuit 302 removes a SYNC detection pulse that is erroneously detected using this synchronization window signal.

  The byte counter 304 generates a byte clock for converting the reproduced binary data, which is serial data, into parallel data. The byte counter 304 is a circuit that counts up an internal counter every time a channel clock is input. At the same time, when there is a pulse input from the synchronization protection circuit 302, the byte counter 304 resets the counter value to zero. The byte counter 304 outputs a pulse when the internal count value reaches 12, and simultaneously resets the count value to zero. The serial / parallel converter 305 converts the serial input reproduction data string into 12-bit parallel data. The output of the byte counter 304 is used for the conversion timing at this time.

  Reference numerals 306 to 313 denote flip-flops. Each time the SYNC number is detected by the SYNC detection circuit 301, the SYNC number is fetched sequentially. That is, the latest SYNC number is stored in the flip-flop 306, the SYNC number one frame before is stored in the flip-flop 307, and the SYNC number seven frames before is stored in the flip-flop 313 in the same manner. The frame number detection unit 314 compares a maximum of eight SYNC numbers with the SYNC number sequence shown in FIG. 16 and outputs the current frame number. Here, the maximum of eight SYNC numbers are used because the SYNC number has a relatively high probability of erroneous detection, and thus robust determination is performed so that erroneous detection of the SYNC number does not affect the frame number. As described above, the SYNC detection / synchronization circuit 111 outputs the frame number and converts the reproduced serial data into parallel data.

  By the way, in the frame structure shown in FIG. 16, SY0 is inserted alone only in the first frame in the sector. That is, if the SYNC number detected by the SYNC detection circuit 301 is SY0, it can be immediately determined that the frame is the 0th frame. That is, when the output of the flip-flop 306 is SY0, the frame number is 0, when the output of the flip-flop 307 is SY0, the frame number is 1 and when the output of the flip-flop 308 is SY0. The frame number 2 is output. In such a case, the error correction process can be started immediately.

  Here, in the first to fourth embodiments, the reproduction operation is started from the VFO area for both the rewritable medium and the reproduction-only medium. 3 and 5, data starting from frame 0 is recorded immediately after the VFO area. Therefore, the SYNC code detected first after the start of the third step of the phase pull-in operation in the first to fourth embodiments should be SY0. Therefore, the frame number detection unit immediately outputs frame number 0 when SY0 is detected before the predetermined time elapses after the start of the third step of the phase pull-in operation. This makes it possible to start an error correction operation without waiting for detection of up to eight SYNC numbers.

As described above, according to the above-described embodiment, it is possible to provide an optical disc apparatus capable of wide capture range and high-speed heading in a rewritable disc medium that performs high-density recording.
Further, according to the above embodiment, it is possible to provide an optical disc apparatus capable of wide capture range and high-speed heading on a read-only disc medium.
Further, according to the above embodiment, it is possible to provide an optical disc apparatus having a wide reading margin by performing adaptive learning at high speed and high accuracy.
Further, according to the above embodiment, it is possible to provide an optical disc apparatus capable of detecting a frame number at high speed and capable of high-speed cueing.

(Other embodiments)
Embodiments of the present invention are not limited to the above-described embodiments, and can be expanded and modified. The expanded and modified embodiments are also included in the technical scope of the present invention.

It is a figure which shows the hierarchical structure of the recording data of the optical disk medium based on one Embodiment of this invention. It is a figure which shows the hierarchical structure of the recording data of the read-only optical disk medium. FIG. 3 is a diagram showing details of a part of recording data of the read-only optical disc medium shown in FIG. 2. It is a figure which shows the hierarchical structure of the recording data of a recordable type optical disk medium. It is a figure which shows the hierarchical structure of the recording data of a rewritable optical disk medium. It is a figure which shows the layout of linking. It is a figure which shows the structure of the recording / reproducing circuit based on the 1st Embodiment of this invention. It is a figure showing an example of the output signal of an optical head. It is a figure which shows the structural example of an adaptive equalization circuit and an adaptive learning circuit. It is a figure showing an example of an address reproduction circuit. It is a figure showing an example of a frequency and phase control circuit. It is a figure showing an example of a VFO pattern phase comparator. It is a figure which shows the structural example of the reproducing | regenerating circuit based on the 2nd Embodiment of this invention. It is a figure showing an example of a VFO area | region detector. It is a figure which shows the structural example of the VFO area | region detector containing a frequency comparison function. It is a figure showing a SYNC frame structure. It is a figure which shows the structural example of a SYNC detection and a synchronous circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Optical disk medium, 101 ... Optical head, 102 ... Sum signal, 103 ... Difference signal, 104 ... High-pass filter, 105 ... Low-pass filter, 106 ... Analog-digital converter, 107 ... Adaptive equalizer, DESCRIPTION OF SYMBOLS 108 ... Frequency / phase control circuit 109 ... Adaptive learning circuit 110 ... Viterbi decoder 111 ... Detection / synchronization circuit 112 ... Demodulation circuit 113 ... Address reproduction circuit 114 ... Recording compensation control circuit 115 ... Modulation circuit DESCRIPTION OF SYMBOLS 116 ... Area | region detection circuit, 120 ... Tracking phase comparator, 121 ... Pattern phase comparator, 122 ... Frequency comparator, 123 ... Changeover switch, 124 ... Loop filter, 125 ... Digital-analog converter, 126 ... Voltage controlled oscillator 129: Counter, 130: Flip-flop

Claims (5)

An optical disk apparatus you play an optical disc medium having a region in which repeat data is recorded in Jo Tokoro,
A rotating mechanism for rotating the optical disk medium;
A light source for irradiating the optical disk medium with light;
A light receiving element for receiving light emitted from the light source and reflected from the optical disk medium;
A reference clock generator for generating a reference clock for the playback of the optical disc medium,
A converter for converting a signal output from the light receiving element into a digital signal based on the reference clock;
Based on the digital signal that corresponds to the repeated data of the predetermined cycle output the transducer or al, anda phase controller for controlling the phase of the reference clock generated by the reference clock generation unit,
The phase control unit is
A signal generator for generating a bit string corresponding to the repetitive data of the predetermined period;
A phase for controlling the phase of the reference clock generated by the reference clock generation unit by determining an arithmetic expression based on a combination of a plurality of consecutive bits of the generated bit string and calculating the digital signal An optical disc apparatus comprising: a phase error information generation unit that generates error information . An area detector for detecting the area based on a signal output from the light receiving element;
The optical disc apparatus according to claim 1, further comprising: The area detector is
A correlation calculation unit for calculating a correlation between a signal output from the light receiving element and a signal before the predetermined clock of the signal;
Based on said correlation of calculated signal by the correlation calculating unit, according to claim 2 Symbol mounting of the optical disk apparatus characterized by having a, a detecting unit for detecting a region. A first correlation calculator for calculating a correlation between a signal output from the light receiving element and a signal before the first predetermined clock of the signal;
A second correlation calculator for calculating a correlation between a signal output from the light receiving element and a signal of the signal before a second predetermined clock different from the first predetermined clock;
A frequency control unit for controlling a clock frequency of the reference clock generation unit based on the calculation results by the first and second correlation calculation units;
Further serial mounting of the optical disk apparatus any one of claims 1 to 3, characterized in that it comprises. The phase error information generation unit generates phase error information at least several times per cycle of the repetitive data.
The optical disc device according to claim 1, wherein the optical disc device is an optical disc device.

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