JPH09147499A - Data detecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device capable of remarkably shortening a seek time by sharing respective means of binarization, oscillation, phase comparison, pattern width detection, oscillation period detection, period comparison, operation and a filter and a frequency loop. SOLUTION: This device is provided with a specified pattern width detection means 6 for obtaining frequency information of a clock component provided in a binary signal and an oscillation period detection means 7 counting the period 16 frequency dividing an oscillation clock of an oscillation means 5 by a fixed clock and obtaining the clock period information. A comparison means 8 compares the 16T period of the binary signal with the 16 frequency division period of the oscillation means 5, and when the 16T period is higher than the 16 frequency division period, operates a pump means 3 so as to heighten the frequency. Conversely, when the 16 frequency division period is higher, the means 5 operates the pump means 3 so as to lower the frequency. Thus, the frequency loop so that the clock of the oscillation means 5 draws the clock component provided in the binary signal in a frequency is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data detection device for detecting reproduction data of a disk device or the like, and more specifically, a reproduction signal of an optical disk medium digitally recorded so that a linear recording density becomes substantially constant. The present invention relates to a phase-locked loop that regenerates a clock component that has.

[0002]

2. Description of the Related Art In recent years, digitization of information has advanced, and it has permeated not only in information-related fields but also in audio-video fields. An optical disc is one of the media attracting attention as a medium for digitally recording such information as voice and image. Optical discs are generally superior to other magnetic tapes and magnetic discs in terms of random accessibility, medium exchangeability, and storability. Constant linear velocity (Const
ant Linear Velocity (CLV) recording method. The CLV recording method is a method that realizes the maximum recording capacity in the same disk size by making the bit recording density constant and maximal throughout the recordable area. In the data reproduction of the CLV recording method, it is usually necessary to change the disk rotation speed according to the radius of the reproduction area, that is, the track in order to keep the reproduction data rate constant. Usually, in order to convert the reproduced signal to digital data, a phase locked loop for the clock component of the reproduced signal is configured, and a frequency loop for motor control that pulls the clock frequency obtained here to a fixed frequency is provided. It is configured so that the reproduction data rate becomes a predetermined rate.

The phase lock loop used for converting a reproduced signal into digital data has a small sync pull-in range of usually 5% or less, and a high-precision rotation speed control according to the track radius is required to perform the sync pull-in. However, there is a problem in establishing synchronization pull-in because it is not easy. After digital modulation that satisfies the (d, k) rule used in the compact disc as an example of the reproduction signal (however, in the compact disc, d = 2, k = 1)
0), and NRZI (Non Return to Z)
ero, Inverse) modulation is performed and code "1"
Pit Width Modulation (Pit Width Modul)
data, the data is reproduced based on the rising and falling edges of the reproduction signal. The clock information of the reproduced data is reproduced using the phase locked loop by utilizing the fact that this edge is obtained at discrete time intervals determined by the (d, k) rule.

FIG. 1 shows a conventional data detecting device.
9 will be described. The data detection device is the optical disc 1
8 and a disk motor 19 for rotating the optical disk 18.
An optical pickup 20 for reproducing the information recorded on the optical disc 18, a binarizing means 1 for binarizing the reproduced signal at a predetermined voltage level and outputting a binary signal, and an output voltage for the low-pass filter means 4. An oscillating means 5 for outputting a clock having a proportional frequency, a phase comparing means 2 for comparing the phases of a binary signal and a clock and outputting a phase error signal, and a charge pump for discharging or sucking current according to the phase error signal. It comprises a means 3, a low-pass filter means 4 for converting the output current of the charge pump means 3 into a voltage and at the same time limiting the band and inputting it to the oscillating means 5, and a motor control means 21 for controlling the motor speed.

The operation of the data detecting apparatus configured as described above will be described below with reference to FIG. The reproduction signal (a) reproduced from the optical disk is binarized by the binarizing means 1 at a predetermined voltage level and converted into a binary signal (b). The oscillating means 5 has a characteristic of oscillating a clock having a frequency proportional to the input voltage, for example, as shown in FIG. 21, and oscillates at the free-running frequency (c) before the synchronization pull-in. The phase comparison means 2 compares the phase of the binary signal with the phase of the oscillation clock. As shown in FIG. 22, when the clock phase is advanced according to the phase relationship of the two inputs, the positive pulse (f) and the binary signal. When the phase is advanced, the negative pulse (g) is output with a time width corresponding to the phase error. The charge pump means 3 outputs positive and negative currents according to the phase error amount. The charge pump means 3 is composed of, for example, current sources I1 and I2 and switches S1 and S2 as shown in FIG. 23. By conducting S1 with a negative pulse, a predetermined current is discharged by the current source I1 and with S2 a positive pulse. A predetermined current is drawn by the current source I2 when the current is turned on. The low-pass filter means 4 is composed of, for example, a resistor R and a capacitance C as shown in FIG. 24, and converts the current output from the charge pump means 3 into a voltage and simultaneously limits the band. The oscillating means 5 oscillates with a clock having a frequency proportional to the voltage generated by the low-pass filter means 4. As described above, when the clock phase of the oscillating means 5 is advanced with respect to the binary signal, a positive pulse is output, current is sucked by the charge pump, and the filter voltage drops, so that the output clock frequency of the oscillating means 5 increases. It becomes low and works in the direction of delaying the clock in phase. On the contrary, when the clock phase of the oscillating means 5 is delayed with respect to the binary signal, a negative pulse is output and the charge pump discharges the current, and the filter voltage rises, so that the output clock frequency of the oscillating means 5 increases. It becomes higher and works in the direction of advancing the clock in phase. In this way, the negative feedback control works, the frequencies of both signals substantially match, and the positive and negative pulse widths finally become small, so that the phase synchronization pull-in of the binary signal (b) and the clock (d) is obtained. Done. Further, when performing CLV control and reproducing data at a fixed transfer rate, the rotation of the motor is controlled so that the oscillation frequency obtained by the oscillation means 5 of the phase locked loop becomes a fixed frequency.

[0006]

[Problems to be Solved by the Invention]
Since the edge information of the value signal is modulated according to the recording data, it does not appear uniformly, and the phenomenon that the phase locked loop is pseudo-locked outside the predetermined frequency occurs. In order to prevent the pseudo lock, it is necessary to adjust the number of rotations of the motor so that the reproduction signal rate becomes almost a predetermined rate.

The narrow lock-in range of this phase-locked loop is that the input data is pulse-modulated data and is temporally scattered information. Therefore, it is impossible to lock in frequency and rely only on phase lock-in. It is due.

As described above, attention must be paid to the lock-in of the phase-locked loop, and there is a problem in realizing a device that does not cause pseudo lock. Therefore, as shown in FIG. 25, the synchronous pull-in circuit requires the motor control means 21 for adjusting the rotation speed of the motor so that the reproduction signal rate is substantially within the synchronous pull-in range. For example, as shown in FIG. 26, the motor control means 21 utilizes that the rising and falling edges of the reproduction signal (a) are obtained at discrete time intervals determined by the (d, k) rule, and the shortest reproduction signal is obtained. A circuit was required to determine the pulse width or the longest pulse width and control the motor rotation so that this pulse width would be a predetermined value. When the pulse width is shorter than the predetermined width as in (h), the disk rotation is fast and the rotation speed is slowed. On the contrary, when it is long as in (i), the disk rotation is slow and the playback signal rate is increased by increasing the rotation speed. The motor speed was controlled so that it was within the phase lock pull-in range.

However, in the above-mentioned conventional configuration, since the response of the motor is slow, it takes time for the disk rotation to fall within the pull-in range of the synchronous circuit, and the ratio of the seek time is large.

Although it is possible to shorten the settling time until the motor rotates steadily, the motor torque and drive current are limited. Also, when controlling the motor rotation by detecting the shortest pulse width or the longest pulse width of the reproduction signal, it is necessary to secure the detection sampling period for a certain time or longer because there is a restriction on the frequency at which the shortest pulse width and the longest pulse width appear. However, it was difficult to increase the control band.

The present invention solves the above-mentioned conventional problems. The shortest or longest pulse width of the reproduced signal is obtained, and at the same time, the output period of the oscillating means 5 is obtained so that the frequency of the oscillating means 5 is phase-locked. It is an object of the present invention to provide a data detection device capable of shortening the time required for synchronization pull-in and significantly shortening the seek time by configuring a frequency loop in which feedback is performed so as to fall within a possible range.

[0012]

A data detection apparatus of the present invention outputs a binary signal by binarizing a reproduced signal at a predetermined level and outputting a binary signal, and a clock signal having a frequency proportional to an input signal. Oscillating means, and phase comparing means for outputting a first difference signal indicating a phase difference between the binary signal and the clock signal by comparing the binary signal and the clock signal, By detecting the time width of the specific pattern included in the binary signal, the specific pattern width detecting means for outputting the first information indicating either the reproduction cycle or the reproduction frequency, and the cycle of the clock signal are detected. Accordingly, by comparing the first information and the second information with an oscillation cycle detecting unit that outputs second information indicating either the oscillation cycle or the oscillation frequency, the first information can be obtained. A cycle comparing means for outputting a second difference signal indicative of the difference between the broadcast and the second information, the first
Of the difference signal and the second difference signal, and a filter means for band-limiting the output of the calculating means and outputting it as the input signal of the oscillating means. Is achieved.

With the above structure, the shortest or longest pulse width of the reproduced signal is obtained, and at the same time, the clock period of the oscillating means is obtained so that the frequency of the oscillating means falls within the range in which the phase synchronization can be pulled in. Clock recovery can be performed at high speed and with certainty by also having a phase synchronization pull-in operation.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a binarizing means for binarizing a reproduced signal at a predetermined level to output a binary signal, and a clock signal having a frequency proportional to the input signal. To output a phase error signal by comparing the phase of the binary signal with the clock signal, and detecting the time width of a specific pattern included in the binary signal. Specific pattern width detection means for outputting cycle (or reproduction frequency) information, and oscillation cycle detection means for outputting oscillation cycle (or oscillation frequency) information by detecting the cycle of the clock signal,
Cycle comparison means for calculating the difference between the reproduction cycle and the oscillation cycle (or the reproduction frequency and the oscillation frequency) from the output of the specific pattern width detection means and the output of the oscillation cycle detection means, and outputting the cycle error signal, the phase error signal and the cycle Comprised of an arithmetic means for inputting an error signal and performing arithmetic according to each signal, and a filter means for band limiting the output of the arithmetic means and outputting as an input signal of the oscillating means,
A phase-locked loop that operates so that the clock signal is phase-locked to the change point edge of the binary signal by the oscillating means, the phase comparing means, the calculating means, and the filtering means, the oscillating means, the specific pattern width detecting means, and the oscillating cycle detecting means. A data detection device that shares a frequency loop that operates so that a clock period becomes substantially the same as a reproduction period by a period comparison unit, a calculation unit, and a low-pass filter unit, and a time width and oscillation of a specific pattern included in a binary signal. The frequency of the clock component of the binary signal and the oscillating frequency of the oscillating means are substantially matched by the frequency loop which feeds back the relative difference between the reproduction rate of the disk reproduction and the oscillating clock rate of the oscillating means by detecting the clock cycle of the oscillating means. Assures that the phase lock loop completes the lock pull-in reliably and at high speed without quasi-phase lock. It has the effect that.

According to a second aspect of the present invention, the specific pattern width detecting means according to the first aspect counts the time width of the specific pattern included in the binary signal with a fixed clock, and is recorded on the disk. The time width of the specified pattern, that is, the reproduction linear velocity information of the disc, is converted into a digital value.

According to a third aspect of the present invention, the oscillation cycle detecting means of the first aspect counts a cycle obtained by dividing the clock signal output from the oscillation means by n (n is a natural number) with the fixed clock. It has a function of converting the oscillation period into a digital value.

According to a fourth aspect of the present invention, the calculating means of the first aspect comprises voltage generating means for inputting the phase error signal and the periodic error signal and outputting a voltage corresponding to each value. , And has a function of converting the phase error amount and the periodic error amount into a voltage.

According to a fifth aspect of the present invention, the arithmetic means of the first aspect comprises charge pump means for discharging or sucking a current proportional to each value with the phase error signal and the periodic error signal as inputs. It has a function of converting the amount of phase error and the amount of periodic error into a current.

According to a sixth aspect of the present invention, in the charge pump means of the fifth aspect, an addition means for inputting the phase error signal and the periodic error signal and outputting a logical sum signal of the both is added to the logical sum signal. It consists of one charge pump that discharges or absorbs a current according to the operation, and adds the phase error amount and the periodic error amount to convert the phase error amount and the periodic error amount into a current value by one charge pump. Have.

According to a seventh aspect of the present invention, in the charge pump means of the fifth aspect, the first charge pump means operates in response to the phase error signal.
And a second charge pump that discharges or sucks a current having a value of, and a second charge pump that discharges or sucks a current having a second value according to the cyclic error signal. It has a function of converting the amount of periodic error into a current value by an independent charge pump.

According to an eighth aspect of the present invention, the charge pump means according to the fifth aspect inhibits the discharging and sucking operations of the current according to the phase error signal, and as a result stops the phase locked loop. Hold control input and a second hold control input for stopping the frequency loop as a result by inhibiting the current discharging and drawing operations according to the synchronization error signal, and further, the first hold control input and the second hold control input. Loop control means for outputting a control signal to the hold control input of the first hold control input and the second hold control input output from the loop control means. Has the action to do.

According to a ninth aspect of the present invention, in the oscillation period detecting means according to the third aspect, a period obtained by dividing the clock signal by n (n is a natural number) is divided by the fixed clock by k (k is a natural number). It counts with a clock that has been circulated, and has the effect of reducing the operation processing speed of the counter and reducing the load on the circuit.

According to a tenth aspect of the present invention, there is further provided a synchronization detecting means for detecting the phase synchronization state of the clock signal and the binary signal of the eighth aspect and outputting a synchronization detection signal,
The loop control means operates the phase locked loop and the frequency loop in response to the sync detection signal, and has an effect of performing optimum pull-in control according to the phase locked state.

According to an eleventh aspect of the present invention, the synchronization detecting means of the tenth aspect detects that the value obtained by integrating the phase error signal is below a predetermined value level, and By using the obtained phase error information for synchronization detection, it has the effect of performing real-time detection.

According to a twelfth aspect of the present invention, the loop control means according to the eighth aspect receives the period error signal as an input and controls the operations of the phase locked loop and the frequency loop according to the value thereof. , Has an effect of performing optimum pull-in control according to the cycle error.

A thirteenth aspect of the present invention is a synchronizing means for inputting the binary signal and the clock signal according to the eighth aspect and outputting reproduced data obtained by synchronizing the binary signal with the clock signal. The clock signal and the reproduction data as an input, further comprising a pattern detection means for detecting the presence and the presence of periodicity of a periodic pattern periodically included in the reproduction data, the loop control means as an input the pattern detection means output, The phase-locked loop and the frequency loop are operated according to the signal, and has an effect of performing the optimum pull-in control according to the detection state of the periodic pattern.

According to a fourteenth aspect of the present invention, in the eighth aspect, the synchronization detecting means for detecting the phase synchronization state of the clock signal and the binary signal and outputting the synchronization detection signal, the binary signal and the clock signal. Means for outputting reproduced data in which the binary signal is synchronized with the clock signal, and the existence and cycle of a periodic pattern which is inputted with the clock signal and the reproduced data and is periodically included in the reproduced data. Further, the loop control means receives the synchronization detection signal and the output of the pattern detection means and operates the phase-locked loop and the frequency loop in response to the signals. It has the effect of performing optimum pull-in control according to the detection state of the periodic pattern.

According to a fifteenth aspect of the present invention, there is provided a synchronizing means for inputting the binary signal and the clock signal according to the eighth aspect and outputting reproduced data in which the binary signal is synchronized with the clock signal. The clock control signal and the reproduction data are input, further comprising pattern detection means for detecting the presence of a periodic pattern periodically included in the reproduction data, and the loop control means receives the periodic error signal and the output of the pattern detection means as input. The phase-locked loop and the frequency loop are operated according to the signal, and has an effect of performing the optimum pull-in control according to the detection state of the periodic error and the periodic pattern.

According to a sixteenth aspect of the present invention, there is further provided a synchronization detecting means for detecting the phase synchronization state of the clock signal and the binary signal and outputting a synchronization detection signal according to the eighth aspect,
The loop control means operates the phase-locked loop and the frequency loop in response to the periodic error signal and the synchronization detection signal, and has an effect of performing optimum pull-in control according to the detected state of the periodic error and the synchronized state.

According to a seventeenth aspect of the present invention, there is provided a synchronization detecting means for detecting the phase synchronization state between the clock signal and the binary signal and outputting the synchronization detection signal according to the eighth aspect, the binary signal and the clock signal. Means for outputting reproduced data in which the binary signal is synchronized with the clock signal, and the existence and cycle of a periodic pattern which is inputted with the clock signal and the reproduced data and is periodically included in the reproduced data. Further, the loop control means receives the cyclic error signal, the synchronization detection signal, and the output of the pattern detection means, and operates the phase locked loop and the frequency loop according to the signals. , Has an effect of performing the optimum pull-in control according to the cyclic error, the synchronization state, and the detection state of the periodic pattern.

According to the eighteenth aspect of the present invention, in the eighth aspect, the loop control means uses the synchronization detection signal or the pattern detection means output as the second hold control input of the charge pump means, and the periodic error signal is the charge pump. First of means
The hold control input of the phase lock loop is disabled until the period error signal is within the specified range, and only the frequency loop is operated when the synchronous error signal is within the specified range. When the synchronous detection signal or the pattern detection means detects a periodic pattern, the frequency loop is prohibited and only the phase-locked loop is operated. The synchronous detection signal or the periodic pattern and the periodic error are generated. Has the effect of performing the optimum pull-in control according to the detection state of.

According to a nineteenth aspect of the present invention, in the eighth aspect, the loop control means uses the synchronization detection signal or the pattern detection means output as the second hold control input of the charge pump means, and the cycle error signal is the charge pump. First of means
The hold control input of the phase lock loop is disabled until the period error signal is within the specified range, and only the frequency loop is operated when the synchronous error signal is within the specified range. When the loops are operated together and the phase synchronization is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detecting means, the frequency loop is prohibited and only the phase synchronization loop is operated. If the phase synchronization is no longer detected or the periodic pattern is no longer detected due to, the phase lock loop and the frequency loop are operated together, depending on the detection state of the synchronization detection signal or the periodic pattern and the periodic error. It has the effect of performing optimum pull-in control.

According to a twentieth aspect of the present invention, in the eighth aspect, the loop control means uses the synchronization detection signal or the pattern detection means output as the second hold control input of the charge pump means, and the cycle error signal is the charge pump. First of means
The hold control input of the phase lock loop is disabled until the period error signal is within the specified range, and only the frequency loop is operated when the synchronous error signal is within the specified range. When the loops are operated together and the phase synchronization is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detecting means, the frequency loop is prohibited and only the phase synchronization loop is operated. When the phase synchronization is not detected by the above or the periodic pattern is not detected by the pattern detecting means, the phase lock loop is prohibited and only the frequency loop is operated. It has the effect of performing optimum pull-in control according to the error detection state.

According to a twenty-first aspect of the present invention, in the eighth aspect, the loop control means uses the synchronization detection signal or the pattern detection means output as the second hold control input of the charge pump means, and the tracking on of the disk drive is turned on. The signal is used as the first hold control input of the charge pump means, and at the time of synchronous pull-in, the phase-locked loop is prohibited when tracking off and only the frequency loop is operated. When the loops are operated together and the phase detection is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated. Signal or periodic pattern and tracking detection status Has the effect of performing the corresponding optimum pull-in control.

According to a twenty-second aspect of the present invention, in the eighth aspect, the loop control means uses the synchronization detection signal or the pattern detection means output as the second hold control input of the charge pump means, and the tracking on of the disk drive is turned on. The signal is used as the first hold control input of the charge pump means, and at the time of synchronous pull-in, the phase-locked loop is prohibited when tracking off and only the frequency loop is operated. When the loops are operated together and the phase synchronization is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detecting means, the frequency loop is prohibited and only the phase synchronization loop is operated. Phase locked loop and frequency if no longer detected Is intended to work together the-loop,
It has the function of performing optimum pull-in control according to the synchronization detection signal or the periodic pattern and the detection state of tracking.

According to a twenty-third aspect of the present invention, in the eighth aspect, the loop control means uses the synchronization detection signal or the pattern detection means output as the second hold control input of the charge pump means, and the tracking on of the disk drive is turned on. The signal is used as the first hold control input of the charge pump means, and at the time of synchronous pull-in, the phase-locked loop is prohibited when tracking off and only the frequency loop is operated. The loops are operated together, and when the phase detection is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated. Phase when no periodic pattern is detected Is intended to only the operating frequency loop prohibits period loop has the effect of performing the optimum pull-in control in accordance with the detected state of the synchronization detection signal or a periodic pattern and tracking.

According to a twenty-fourth aspect of the present invention, in the fifth aspect, the charge pump means sucks or discharges a predetermined current according to the polarity of the cycle error signal output from the cycle comparison means at every predetermined cycle. It is performed for a predetermined time, and has an action of determining the gain in the frequency loop in a predetermined manner by controlling the time for sucking or discharging the current.

According to a twenty-fifth aspect of the present invention, in the fifth aspect, the charge pump means outputs a current proportional to a cycle error signal output from the cycle comparison means for a predetermined time every predetermined cycle. By controlling the amount of current, it has the effect of determining the gain in the frequency loop in a form proportional to the frequency error.

According to a twenty-sixth aspect of the present invention, in the fifth aspect, the charge pump means absorbs or discharges a predetermined current according to the polarity of the cycle error signal output from the cycle comparison means at every predetermined cycle. This is performed by controlling the time width in proportion to the absolute value of the periodic error signal, and has the effect of determining the gain in the frequency loop in a form proportional to the frequency error by controlling the current suction and discharge times.

According to a twenty-seventh aspect of the present invention, in the first aspect, the phase comparison means outputs the period detector which outputs a signal proportional to the oscillation period of the oscillation means, and outputs the binary signal from the period detector. , A pulse gate circuit for outputting clock edge information of oscillation output only when there is a binary signal input, and a phase difference between the delay device output and the pulse gate means output. And a phase difference detector for generating two pulses representing positive or negative depending on the sign of the phase difference with a pulse width corresponding to the amount of phase difference, and the delay amount of the delay device is The present invention is characterized in that control is performed in proportion to the oscillation cycle, and by controlling the delay amount of the phase comparator in proportion to the oscillation cycle of the oscillating means, the positive and negative phase comparison range is symmetric to -π to + π. Has the effect of

According to a twenty-eighth aspect of the present invention, in the twenty-seventh aspect, the delay amount of the delay device is controlled in proportion to the oscillation period of the oscillating means and can be held by an external signal. Even when the clock frequency fluctuates due to a disturbance such as out, the phase comparison operation is stabilized by detecting this and holding the delay amount of the phase comparator.

According to a twenty-ninth aspect of the present invention, in the twenty-seventh aspect, the delay amount of the delay device is controlled in proportion to the oscillation cycle of the oscillating means, and the delay amount can be switched to a predetermined delay amount by an external signal. Even if the clock frequency fluctuates due to external disturbance such as dropout, it has the effect of stabilizing the phase comparison operation by detecting this and returning the delay amount of the phase comparator to the default value. .

According to a thirtieth aspect of the present invention, in the twenty-seventh aspect of the present invention, the delay amount of the delay device is controlled in proportion to a current or voltage proportional to the oscillation cycle of the oscillating means, which is reduced and filtered. Therefore, it has the effect of stabilizing the phase comparison operation without being affected by the high frequency fluctuation of the oscillation means.

According to a thirty-first aspect of the present invention, in the first aspect, the phase comparison means is a digital-analog converter which outputs a current or a voltage proportional to the reproduction period information obtained by the specific pattern width detection means. A delay device for providing a delay proportional to the output of the digital-analog converter,
The phase difference between the output of the oscillating means and the output of the clock edge information only when there is a binary signal input is compared with the phase difference between the output of the delay device and the output of the pulse gate means, and a positive value is obtained according to the sign of the phase difference. Alternatively, a phase difference detector that generates two negative pulses with a pulse width corresponding to the phase difference amount, and controls the delay amount of the delay device in proportion to the count value of the specific pattern width detecting means. By controlling the delay amount of the phase comparator in proportion to the cycle of the clock component of the reproduction signal, the positive and negative phase comparison range is symmetric to −π to + π.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The data detection device of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 shows a block diagram of a data detection device. The data detecting device comprises a binarizing means 1 for binarizing a reproduced signal at a predetermined voltage level and outputting a binary signal, an oscillating means 5 for outputting a clock having a frequency proportional to the output voltage of the low pass filter means 4, Phase comparison means 2 for comparing the phase of a binary signal and a clock and outputting a phase error signal, charge pump means 3 for discharging or sucking current according to the phase error signal, and charge pump means output current converted to voltage. At the same time, the low-pass filter means 4 for limiting the band and the specific pattern detecting means 6 for counting the length of a specific pattern, for example, the longest mark included in the binary signal with a fixed clock and outputting the counting result.
And an oscillation cycle detecting means 7 which counts the oscillation cycle of the oscillation means 5 with a fixed clock and outputs a counting result, and a count output value of the oscillation cycle detecting means 6 and a count output value of the specific pattern width detecting means 6. Then, it comprises a period comparing means 8 which outputs the period error signals of both.

Next, the operation of the first data detector will be described with reference to FIG. FIG. 2 shows a steady reproduction state. The reproduction signal is a signal obtained by reproducing the disc recorded by CLV by pit width modulation. The reproduced signal (a) is binarized at a predetermined level by the binarizing means 1 to become a binary signal (b). To reproduce data from a binary signal,
It is necessary to extract a clock component that is phase-synchronized with this, but due to the characteristics of digital modulation, the edge interval of a binary signal is an integral multiple of the clock cycle and takes a discrete value depending on the recording data, resulting in a spectrum of the binary signal. Since it is spread, it is difficult to detect the frequency component, and the binarization unit 1, the phase comparison unit 2, the charge pump unit 3, the low-pass filter unit 4,
The phase-locked loop composed of the oscillating means 5 cannot perform frequency-dependent pull-in, and only relies on the phase-locked pull-in. The principle of the phase lock pull-in is as described in the conventional example.

Therefore, in order for the binary signal and the clock to be phase-synchronized, the frequency of the clock component of the binary signal and the output clock frequency of the oscillating means 5 have an accuracy of about ± 5% before entering the phase synchronization pull-in. Must match. When the two are greatly different in frequency, they cannot be pulled in to the regular frequency and may be pulled in to the pseudo stable point, so normal synchronization pull-in cannot be expected.

For example, the maximum edge interval of a binary signal corresponds to 16 times the clock period (expressed as 16T, where T is 1).
Clock period), the maximum value of the edge interval of the binary signal is counted with a fixed clock every predetermined detection period in order to prevent the above-mentioned pseudo pull-in.
A specific pattern width detecting means 6 for obtaining cycle information of a clock component of a binary signal from this count value, and a cycle obtained by dividing the oscillation clock 16 of the oscillation means 5 by a fixed clock to obtain clock cycle information. The oscillation cycle detecting means 7 is provided, and the cycle comparing means 8 compares the 16T cycle of the binary signal with the 16-divided cycle of the oscillating means 5 based on these two counting results. The 16T cycle is 16 minutes. When it is larger than the cycle, that is, when the frequency of the oscillating means 5 is lower than the frequency of the clock component of the binary signal, the charge pump means 3 is operated so as to increase the frequency of the oscillating means 5, and vice versa. Further, when the 16-cycle period of the clock of the oscillation means 5 is smaller than the 16T cycle of the binary signal, that is, when the frequency is high, the frequency of the oscillation means 5 is lowered. By operating the pump means 3, constitute a frequency loop as draw in frequency the clock component oscillation clock oscillating means 5 has a binary signal.

FIG. 3 shows the operation of the frequency / phase locked loop. First, since the frequency of the clock component of the binary signal is far from the frequency of the oscillation means 5 (point A), the frequency loop is operated before the operation of the phase locked loop and the frequency and oscillation of the clock component of the binary signal. If the frequency deviation of the clock frequency of the means 5 is within the range of phase lock pull-in, that is, within about ± 5%, and the phase lock loop is operated from point B, normal pull-in is possible without pseudo pull-in. Is. (Point C) The accuracy of frequency acquisition depends on the frequency of the fixed clock, and the higher the frequency of the fixed clock, the higher the detection accuracy. Therefore, it is necessary to determine a fixed clock frequency according to the phase synchronization pull-in range. When a modulation rule in which the maximum edge interval of a binary signal is 16 times (16T) the clock cycle is used, the frequency of the fixed clock used for counting is doubled the oscillation clock frequency of the oscillation means 5 during steady rotation. If set, the detection accuracy is 1/32 = about 3.1%
Accuracy of ± 5% of the phase lock pull-in range
Can be fully met.

However, the detection cycle of the specific pattern detection means 6 must include the maximum edge interval of the binary signal at least once. For example, when the rotation of the disk changes to ½ of the normal rotation due to seeking during disk playback, the maximum edge interval appearance probability is 1/2.
Therefore, it is necessary to have a double detection cycle.

Further, by detecting the maximum value or the minimum value (the minimum value in the above embodiment) of a plurality of adjacent detection sections in the detection of the specific pattern width, the detection error due to the occurrence of a defect on the disk can be reduced. be able to.

The maximum edge interval of the binary signal is 16T.
However, other edge intervals, for example, a recording mark of 14T may be used, and (14T + 4T).
It is also possible to add adjacent edge intervals together in the form of the recording marks and count this interval.

As described above, according to the present embodiment, the phase locked loop and the frequency loop are provided, and the frequency of the clock component of the binary signal and the oscillation of the oscillating means 5 are generated by the frequency loop before the operation of the phase locked loop is started. Since the frequencies are almost the same, the phase-locking operation can be performed reliably without pseudo-phase-locking. Also, as in the conventional method, the rotation of the motor is adjusted and then the phase-locked loop is operated and pulled in. Unlike the above, since the reproduction data rate and the oscillating frequency of the oscillating means 5 are brought close to each other by the frequency loop before the motor enters the steady rotation, the phase synchronization pull-in can be greatly shortened.

Here, both the specific pattern width detecting means 6 and the oscillation cycle detecting means 7 detect the cycle by counting with a fixed clock, but the output clock of the oscillating means 5 is used as the counting clock of the specific pattern width detecting means 6. Even if is used, the relative size of the specific pattern width and the oscillation clock period can be known, and the same operation can be performed. However, in this case, the detection cycle depends on the existence probability of the specific pattern, and in general, the probability of appearance of the specific pattern is low, so the detection cycle becomes long, which limits the control band, and the advantage diminishes. . Since the specific pattern width detection detects a binary signal, that is, a signal obtained from the disc reproduction signal, the variation in the detection value of the specific pattern width is similar to the response of the disc motor and is about several tens Hz, and the sampling frequency for detection is Anything is acceptable. For example, if the appearance frequency of the specific pattern is 1 kHz, it is not a problem because the response speed of the motor is sufficiently high. The response band of the oscillating means 5 is usually set to about several tens KHz, although it depends on the design of the synchronous loop, and thus the fluctuation of the detected value of the oscillation clock cycle is similar to this, and the sampling frequency of the detection is at least according to the sampling theorem. At least twice the response band is required.

If the output clock of the oscillating means 5 is used as the counting clock of the specific pattern width detecting means 6 and the relative magnitude relationship between the specific pattern width and the oscillating clock cycle is known, the cycle of the oscillating means 5 will be determined. Since the detection cycle is substantially the same as the detection cycle of the specific pattern detection, it is unreasonable to control the oscillating means 5 based on this detection result.

If the method of measuring the oscillation clock period of the oscillation means 5 with a fixed clock as shown in FIG. 1 is used, the 16-division cycle of the oscillation means 5 (for example, the predetermined data rate is 25 MHz and the maximum edge interval of the binary signal is the clock). If a modulation rule that is 16 times the period is used, the oscillation period can be detected at 640 ns), and a sufficient sampling frequency for the response of the oscillation means 5 can be realized. Based on this detection result, the oscillation means 5 can be controlled sufficiently, and by constructing the frequency loop as described in the first embodiment, it is possible to achieve both the pull-in time reduction and the control stability. .

Further, since the low-pass filters of the phase locked loop and the frequency loop are shared, the shock at the time of switching is absorbed here, and smooth loop switching can be realized.

In the first embodiment, the charge pump means is composed of one charge pump. However, as shown in FIG. 4, the first charge pump for the phase locked loop and the second charge pump for the frequency loop are used. May be provided independently. As a result, the gain settings of the phase locked loop and the frequency loop can be set independently, and the degree of freedom in loop design can be expanded.

Further, the frequency loop and the phase locked loop are stopped by prohibiting the current output of the charge pump. As shown in FIG. 5, the loop control means 9 for switching the loop operation outputs the first signal. Each loop may be controlled by the first hold signal for inhibiting the output of the first charge pump and the second hold signal for inhibiting the output of the second charge pump.

Further, in the specific pattern width detecting means 6, the clock output from the oscillating means 5 and the fixed clock for counting may be divided and then detected as shown in FIG. As a result, the operating frequency of the counting circuit can be suppressed to a low level, and the detection accuracy can be increased by increasing the frequency division ratio of the oscillation means 5 as compared with the frequency division ratio of the fixed clock.

Further, as shown in FIG. 7, the loop control means 9 determines the first hold signal and the second hold signal for inhibiting the outputs of the first charge pump and the second charge pump based on the cyclic error signal. Something may occur. When the cycle error is large, the operation of the phase-locked loop is stopped by the first hold signal and only the frequency loop is operated so that the cycle of the clock component of the binary signal and the clock cycle of the oscillating means 5 become asymptotic, and the cycle error is reduced. If it is within the phase lock pull-in range, the first hold signal is released and the phase lock loop is operated, and when the phase lock loop pulls in,
For example, when the cycle error becomes zero, the second hold signal inhibits the second charge pump output to stop the operation of the frequency loop, so that the reliable pull-in operation can be performed. The frequency loop may be instantaneously switched to the phase locked loop, but more reliable and smooth switching is possible by creating a state in which both are operating at the time of switching.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. A block diagram of the data detection device is shown in FIG. In FIG. 8, the data detection device includes a binarizing means 1 for binarizing a reproduction signal at a predetermined voltage level and outputting a binary signal, and a low pass filter means 4.
Oscillator 5 for outputting a clock having a frequency proportional to the output voltage of V, phase comparator 2 for comparing the phase of a binary signal and a clock and outputting a phase error signal, and discharging or sucking current according to the phase error signal. And a low-pass filter means 4 for converting the output current of the charge pump means into a voltage and simultaneously limiting the band.
And a specific pattern included in the binary signal, for example, the length of the longest mark is counted with a fixed clock and a counting result is output, and the oscillation cycle of the oscillator 5 is counted with a fixed clock and counted. The oscillation cycle detecting means 7 for outputting the result and the cycle comparing means 8 for comparing the count output values of the count output values of the specific pattern width detecting means 6 and the oscillation cycle detecting means 7 and outputting the cycle error signals of both of them have been described above. The configuration is the same as that of 1. Here, further, the synchronizing means 10 for synchronizing the binary signal with the output clock of the oscillating means 5 to generate the reproduced data synchronized with the clock, and the output clock of the oscillating means 5 and the reproduced data are input to the reproduced data. It is configured by adding pattern detecting means 11 for detecting the locked state of the phase locked loop by detecting the fixed pattern included therein.

The pattern detection means 11 is, for example, a synchronization mark for synchronizing the entire data recorded in the reproduction data at regular intervals, and detects the presence of a fixed pattern and the periodicity. This is performed by reading the reproduced data output from the converting means 10 with the clock of the oscillating means 5.

The cycle of the clock component of the binary signal,
The fixed pattern is not detected when the cycle of the output clock of the oscillating means 5 is different, but the fixed pattern is detected when the cycle becomes asymptotically, and the detected cycle of the fixed pattern in the phase locked state is the output clock cycle of the oscillating means 5. When counted, it becomes a predetermined count value. However, when the phase is not locked, the cycle, that is, the cycle in which the fixed pattern is detected does not reach the predetermined count cycle due to a slight deviation in frequency. Therefore, if the fixed pattern is detected and the period in which the fixed pattern is detected is a predetermined period, it can be determined that the phase synchronization state is established.

The operation of the data detection device of FIG. 8 will be described. The basic synchronization pull-in method is the same as in the first embodiment. When the cycle error is large, the operation of the phase locked loop is stopped and only the frequency loop is operated to operate the cycle of the clock component of the binary signal and the oscillation means 5.
The clock cycle of the asymptotic clock, and if the cycle error falls within the phase lock pull-in range, the phase lock loop is further operated, and when the pattern detection device 11 confirms the lock of the phase lock loop, the second hold signal Disables the charge pump output of and stops the frequency loop operation. FIG. 7 shows the operation sequence of the frequency loop and the phase locked loop in the second embodiment.

In this way, the reliability can be improved by performing the switching from (frequency loop + phase locked loop) to (phase locked loop) with high accuracy using the pattern detection means 11.

In the second embodiment, switching from (frequency loop) to (frequency loop + phase locked loop) is judged by looking at the period error, but it can be replaced with a tracking on signal of the disk drive or the like. Is. Also, switching from (frequency loop + phase-locked loop) to (phase-locked loop) is performed by confirming the synchronization pull-in by pattern detection. For example, this is the default value when the absolute value of the phase error signal is integrated. Any other method may be used as long as it is a means for confirming the synchronization state of the phase locked loop, such as determining that it is in the synchronization state if it is below the level.

Further, in FIG. 9, the sequence ends when the operation is switched to only the phase-locked loop, but a large phase error signal is generated when a signal is missing due to a defect on the disk, and the phase-locked loop is generated. It may come off. When the frequency is largely deviated, it cannot be recovered only by the phase locked loop, so when the pattern cannot be detected, the frequency / phase locked loop is once operated as shown in the operation sequence diagram of FIG. Alternatively, as shown in the operation sequence diagram of FIG. 9, the operation of the phase locked loop may be temporarily stopped and only the frequency loop may be operated. As a result, the ability to recover from disturbance can be improved.

The charge pump means of the first and second embodiments draws in a predetermined current according to the polarity of the cycle error signal output from the cycle comparison means at every predetermined cycle as shown in FIG. Alternatively, the discharge may be performed for a predetermined time.

The charge pump means of the first and second embodiments outputs a current proportional to the cycle error signal output from the cycle comparison means for a predetermined time every predetermined cycle as shown in FIG. It can be one.

The charge pump means of the first and second embodiments draws in a predetermined current according to the polarity of the cycle error signal output from the cycle comparison means at every predetermined cycle as shown in FIG. Alternatively, the discharging may be performed by controlling the time width in proportion to the absolute value of the cyclic error signal.

The phase comparison means 2 delays the binary signal in proportion to the output of the oscillation cycle detection means and the cycle detector 12 which outputs a signal proportional to the oscillation cycle of the oscillation means as shown in FIG. For comparing the phase difference between the output of the delay unit 13 and the output of the pulse gate circuit and the pulse gate circuit 14 for outputting the clock edge information of the oscillation output only when there is a binary signal input. And a phase difference detector 15 for generating two pulses representing positive or negative depending on the sign of the phase difference with a pulse width corresponding to the amount of phase difference.
A signal obtained by allowing the pulse gate circuit 14 to output the clock of the oscillating means 5 only when there is an edge input of the value signal and delaying the binary signal by, for example, a half cycle of the oscillation clock by the delay device 13, The phase difference detector 15 compares the phases of the oscillation clocks. The delay amount of the delay device 13 is controlled in proportion to the oscillation cycle of the oscillating means so that the detection window of the phase difference detector 15 is maximized. By doing so, the detection offset and detection of the phase difference detector 15 are performed. Since the dead zone can be eliminated, the phase synchronization range can be maximized.

The delay amount of the delay device 13 may be controlled in proportion to the oscillation cycle of the oscillation means 5 as shown in FIG. 16 and can be held by an external signal. It is possible to prevent the phase error signal from being disturbed by holding the delay amount of the delay device 13 by a detection signal such as a defect on the disk. Further, the delay amount of the delay device 13 may be controlled in proportion to the oscillation cycle of the oscillating means 5 as shown in FIG. 16, and can be switched to a predetermined delay amount by an external signal. The phase error signal can be prevented from being disturbed by setting the delay amount of the delay device 13 to a predetermined value by a detection signal such as a defect on the disk.

Further, the delay amount of the delay unit 13 may be controlled in proportion to the current or voltage proportional to the oscillation period of the oscillating means 5 which is reduced and filtered by the filter means 16 as shown in FIG. By performing low-pass filtering, it is possible to prevent the delay amount from changing unnecessarily with respect to disturbance.

The phase comparison means 8 is proportional to the digital-analog converter 17 for outputting a current or voltage proportional to the count value of the specific pattern width detector as shown in FIG. 18, and the output of the digital-analog converter 17. And a pulse gate circuit 14 for permitting the output of the clock of the oscillating means 5 only when there is an edge input of a binary signal, and only when there is an edge input of a binary signal. Oscillating means output: pulse gate means for outputting clock edge information, delay device 13 output, and pulse gate circuit 1
The phase difference detector 15 is configured to compare the four phase differences of the four outputs and generate two pulses representing positive or negative depending on the sign of the phase difference with a pulse width corresponding to the amount of phase difference. Delay device 1
The delay amount of 3 is controlled in proportion to the count value of the specific pattern width detector so that the detection window of the phase difference detector 15 spreads to the maximum, and by doing so, the detection offset of the phase difference detector 15, Since the detection dead zone can be eliminated, the phase synchronization range can be maximized.

Further, the phase comparison means 8 may have a configuration other than the above as long as it can realize the phase comparison operation.

In the first and second embodiments, the CLV-recorded disc has been described, but any other recording method, such as a recording system, can be used as long as the reproduction linear velocity information of the disc can be obtained from the recorded data. It may be CAV recording.

The charge pump means of the first and second embodiments has been described as a current drive type charge pump which outputs a current in response to a phase error signal. A voltage drive type configuration that outputs a voltage may be used.

Further, in the first embodiment, the binarizing means for binarizing the reproduction signal of the optical disk is used, but waveform equalization for reducing the intersymbol interference of the reproduction signal and improving the signal-to-noise ratio is performed. Needless to say, it may be binarized after being played.

[0082]

As described above, according to the present invention, the oscillation period of the oscillating means and the time width of the specific pattern included in the binary signal are detected even when the phase lock loop is out of the lock-in range. The frequency loop is constructed by performing feedback control of the above, and an effective effect that the pulling operation can be performed at high speed, reliably and smoothly is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data detection device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the data detection device according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of a frequency / phase locked loop.

FIG. 4 is a block diagram of charge pump means independent of a frequency loop and a phase loop.

FIG. 5 is a block diagram of charge pump means capable of switching loop operations.

FIG. 6 is a block diagram of specific pattern detection means.

FIG. 7 is a diagram showing input / output signals of a loop control means.

FIG. 8 is a block diagram of a data detection device according to a second embodiment of the present invention.

FIG. 9 is a diagram showing an operation sequence of a frequency / phase locked loop.

FIG. 10 is a diagram showing an example of an operation sequence when a disturbance occurs.

FIG. 11 is a diagram showing an example of an operation sequence when a disturbance occurs.

FIG. 12 is a diagram showing an output signal during operation of the charge pump means.

FIG. 13 is a diagram showing an output signal during operation of the charge pump means.

FIG. 14 is a diagram showing an output signal during operation of the charge pump means.

FIG. 15 is a block diagram of phase comparison means.

FIG. 16 is a diagram showing input / output signals of a delay device.

FIG. 17 is a block diagram connecting a delay device and an oscillating means.

FIG. 18 is a block diagram of phase comparison means.

FIG. 19 is a block diagram of a conventional data detection device.

FIG. 20 is a diagram for explaining the operation of the conventional data detection device.

FIG. 21 is a characteristic diagram showing an example of input voltage versus output frequency characteristics of the oscillating means.

FIG. 22 is a diagram for explaining the operation of the phase comparison means.

FIG. 23 is a circuit diagram of charge pump means.

FIG. 24 is a circuit diagram of low-pass filter means.

FIG. 25 is a diagram showing a motor control process until phase synchronization.

FIG. 26 is a diagram for explaining the motor control operation.

[Explanation of symbols]

 1 Binarizing Means 2 Phase Comparing Means 3 Charge Pump Means 4 Low Pass Filter Means 5 Oscillating Means 6 Specific Pattern Width Detecting Means 7 Oscillation Cycle Detecting Means 8 Cycle Comparing Means 9 Loop Control Means 10 Synchronizing Means 11 Pattern Detecting Means 12 Cycle Detecting Means Means 13 Delay device 14 Pulse gate circuit 15 Phase difference detector 16 Low-pass filter 17 Digital-analog converter 18 Optical disk 19 Disk motor 20 Optical pickup 21 Motor control means

Front page continuation (72) Inventor Hiroyuki Miyaji 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (31)

[Claims] 1. A data detection device for reproducing digital information modulated and recorded with a discrete recording length, which comprises binarizing means for binarizing a reproduced signal at a predetermined level and outputting a binary signal. A first difference indicating a phase difference between the binary signal and the clock signal by comparing the binary signal and the clock signal with an oscillating unit that outputs a clock signal having a frequency proportional to the signal. A phase comparison unit that outputs a signal, and a specific pattern width detection unit that outputs the first information indicating either the reproduction cycle or the reproduction frequency by detecting the time width of the specific pattern included in the binary signal. And an oscillation cycle detecting means for outputting second information indicating either the oscillation cycle or the oscillation frequency by detecting the cycle of the clock signal, the first information and the second information. Cycle comparing means for outputting a second difference signal indicating a difference between the first information and the second information by comparing the information with the first information; Computation means for performing computation in accordance with the difference signal, and filter means for band-limiting the output of the computation means and outputting it as the input signal of the oscillation means, the oscillation means, the phase comparison means, the computation means, and the A phase-locked loop that operates so that the clock signal is phase-locked with the change point edge of the binary signal by the filter means, the oscillation means, the specific pattern width detection means, the oscillation cycle detection means, the cycle comparison means, and the calculation. And a low-pass filter that shares a frequency loop that operates so that a clock cycle is substantially the same as a reproduction cycle. 2. The data detecting apparatus according to claim 1, wherein the specific pattern width detecting means counts the time width of the specific pattern included in the binary signal with a fixed clock. 3. The oscillation cycle detection means counts a cycle obtained by dividing a clock signal output from the oscillation means by n (n is a natural number) with the fixed clock. Data detector. 4. The calculation means is voltage generation means for receiving the first difference signal and the second difference signal and outputting a voltage according to the first difference signal and the second difference signal. The data detection device according to claim 1, wherein 5. The charge pump means for receiving the first difference signal and the second difference signal and discharging or sucking a current according to the first difference signal and the second difference signal. The data detection device according to claim 1, wherein 6. The charge pump means receives the first difference signal and the second difference signal,
An addition unit that outputs a logical sum signal of the first difference signal and the second difference signal, and one charge pump that discharges or sucks a current according to the logical sum signal are provided. The data detection device according to claim 5. 7. The charge pump means includes a first charge pump that discharges or sucks a current having a first value according to the first difference signal, and a first charge pump that responds to the second difference signal. The data detection device according to claim 5, further comprising a second charge pump that discharges or sucks a current having a value of 2. 8. The charge pump means comprises a first hold control input for stopping a phase-locked loop as a result by prohibiting a current discharging and drawing operation in response to the first difference signal, and the second hold control input. A second hold control input that results in stopping the frequency loop by prohibiting current source and sink currents in response to the difference signal between the first hold control input and the second hold control input. 6. The data detection device according to claim 5, further comprising: a loop control unit that outputs 9. The oscillation cycle detecting means counts a cycle obtained by dividing a clock signal by n (n is a natural number) by a clock obtained by dividing the fixed clock by k (k is a natural number). The data detection device according to claim 3. 10. A synchronization detection unit that detects a phase synchronization state of the clock signal and the binary signal and outputs a synchronization detection signal, wherein the loop control unit includes the phase synchronization unit according to the synchronization detection signal. The data detection device according to claim 8, wherein a loop and the frequency loop are operated. 11. The data according to claim 10, wherein the synchronization detecting means detects that a value obtained by integrating an absolute value of the first difference signal is below a predetermined value level. Detection device. 12. The data detection device according to claim 8, wherein the loop control means controls operations of the phase locked loop and the frequency loop according to the second difference signal. 13. Synchronizing means for receiving the binary signal and the clock signal and outputting reproduction data obtained by synchronizing the binary signal with the clock signal, and receiving the clock signal and the reproduction data, and reproducing the reproduction data. Pattern detection means for detecting the presence and the presence or absence of periodicity of a periodic pattern periodically included in the data, wherein the loop control means comprises the phase-locked loop according to a signal output from the pattern detection means. 9. The data detection device according to claim 8, wherein the frequency loop is operated. 14. A synchronization detecting unit that detects a phase synchronization state of the clock signal and the binary signal and outputs a synchronization detection signal, and the binary signal and the clock signal, and receives the binary signal by the clock. Synchronizing means for outputting reproduced data synchronized with the signal, pattern detecting means for receiving the clock signal and the reproduced data, and detecting the presence of a periodic pattern periodically included in the reproduced data and the presence or absence of periodicity 9. The loop control means further operates the phase locked loop and the frequency loop according to the synchronization detection signal and the signal output from the pattern detection means. Data detector. 15. Synchronizing means for receiving the binary signal and the clock signal and outputting reproduction data obtained by synchronizing the binary signal with the clock signal, and receiving the clock signal and the reproduction data, and reproducing the reproduction signal. Pattern detection means for detecting the presence of a periodic pattern periodically included in the data, wherein the loop control means is responsive to the second difference signal and the signal output from the pattern detection means. 9. The data detection device according to claim 8, wherein the phase locked loop and the frequency loop are operated. 16. A synchronization detection unit that detects a phase synchronization state of the clock signal and the binary signal and outputs a synchronization detection signal, wherein the loop control unit includes the second difference signal and the synchronization detection unit. 9. The data detection device according to claim 8, wherein the phase locked loop and the frequency loop are operated according to a signal. 17. A synchronization detecting unit that detects a phase synchronization state of the clock signal and the binary signal and outputs a synchronization detection signal; and a synchronization detecting unit that receives the binary signal and the clock signal.
Synchronizing means for outputting reproduction data in which a value signal is synchronized with the clock signal; existence of a periodic pattern periodically included in the reproduction data for receiving the clock signal and the reproduction data and presence / absence of periodicity Pattern detecting means for detecting the phase-locked loop and the frequency loop according to the second difference signal, the synchronization detection signal, and the signal output from the pattern detection means. The data detection device according to claim 8, wherein the data detection device is operated. 18. The loop control means uses the synchronization detection signal or a signal output from the pattern detection means as the second hold control input of the charge pump means, and uses the second difference signal as the charge pump. The first hold control input of the means, when synchronizing pull-in, until the second difference signal is within a predetermined range, the phase locked loop is prohibited and only the frequency loop is operated. If it is within a predetermined range, the phase locked loop and the frequency loop are operated together,
9. The data detecting apparatus according to claim 8, further comprising: prohibiting the frequency loop and operating only the phase-locked loop when a periodic pattern is detected by the synchronization detection signal or the pattern detection means. 19. The loop control means uses the synchronization detection signal or a signal output from the pattern detection means as the second hold control input of the charge pump means, and uses the second difference signal as the charge pump. The first hold control input of the means, when synchronizing pull-in, until the second difference signal is within a predetermined range, the phase locked loop is prohibited and only the frequency loop is operated. If it is within a predetermined range, the phase locked loop and the frequency loop are operated together,
Further, when phase synchronization is detected by the synchronization detection signal or a periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated, and the phase is detected by the synchronization detection signal. 9. The data detection device according to claim 8, wherein when the synchronization is no longer detected or the periodic pattern is no longer detected, the phase locked loop and the frequency loop are operated together. 20. The loop control means uses the synchronization detection signal or a signal output from the pattern detection means as the second hold control input of the charge pump means, and uses the second difference signal as the charge pump. The first hold control input of the means, when synchronizing pull-in, until the second difference signal is within a predetermined range, the phase locked loop is prohibited and only the frequency loop is operated. If it is within a predetermined range, the phase locked loop and the frequency loop are operated together,
Further, when phase synchronization is detected by the synchronization detection signal or a periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated, and the phase is detected by the synchronization detection signal. 9. The data according to claim 8, wherein when the synchronization is no longer detected or the periodic pattern is no longer detected by the pattern detecting means, the phase locked loop is prohibited and only the frequency loop is operated. Detection device. 21. The loop control means uses the synchronization detection signal or a signal output from the pattern detection means as the second hold control input of the charge pump means, and uses a tracking-on signal of a disk drive as the charge pump. The first hold control input of the means is provided. When the lock-in is performed, the phase-locked loop is prohibited during tracking-off and only the frequency loop is operated. The frequency loop is operated together, and when the phase detection is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated. The data inspection according to claim 8, wherein Apparatus. 22. The loop control means uses the synchronization detection signal or a signal output from the pattern detection means as the second hold control input of the charge pump means, and uses a tracking-on signal of a disk drive as the charge pump. The first hold control input of the means is provided, and when the lock-in is performed, the phase-locked loop is prohibited at the time of tracking off and only the frequency loop is operated. The frequency loop is operated together, and when the phase synchronization is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated, No more periodic patterns detected Data detecting apparatus according to claim 8, characterized in that for operating both the phase lock loop and the frequency loop in case. 23. The loop control means uses the synchronization detection signal or the signal output from the pattern detection means as the second hold control input of the charge pump means, and uses a tracking on signal of a disk drive as the charge pump. The first hold control input of the means is provided, and when the lock-in is performed, the phase-locked loop is prohibited at the time of tracking off and only the frequency loop is operated. The frequency loop is operated together, and when the phase synchronization is detected by the synchronization detection signal or the periodic pattern is detected by the pattern detection means, the frequency loop is prohibited and only the phase synchronization loop is operated, Furthermore, the pattern detection means described above periodically Data detecting apparatus according to claim 8, characterized in that to operate only the frequency loop prohibits the phase locked loop if the over down is no longer detected. 24. The charge pump means carries out a predetermined current suction or discharge for a predetermined time in accordance with the polarity of the second difference signal output from the cycle comparison means at every predetermined cycle. The data detection device according to claim 5. 25. The data according to claim 5, wherein the charge pump means outputs a current proportional to the second difference signal output from the cycle comparison means for a predetermined time every predetermined cycle. Detection device. 26. The charge pump means absorbs or discharges a predetermined current in accordance with the polarity of the second difference signal output from the cycle comparison means at every predetermined cycle, and detects the absolute value of the second difference signal. The data detecting apparatus according to claim 5, wherein the data detecting apparatus is controlled by a time width proportional to the value. 27. The phase comparison means includes a cycle detector that outputs a signal proportional to an oscillation cycle of the oscillation means, and a delay that delays the binary signal in proportion to a signal output from the cycle detector. Comparing the phase difference between the output of the delay unit and the output of the pulse gate means with a pulse gate circuit that outputs the clock edge information of the oscillation output only when the binary signal is input. And a phase difference detector for generating two pulses representing positive or negative depending on the sign of the phase difference with a pulse width corresponding to the amount of phase difference. The delay amount of the delay unit is the oscillation cycle of the oscillating means. The data detection device according to claim 1, wherein the data detection device is controlled in proportion to 28. The data detecting apparatus according to claim 27, wherein the delay amount of the delay device is controlled in proportion to the oscillation cycle of the oscillating means, and can be held by an external signal. 29. The data according to claim 27, wherein the delay amount of the delay device is controlled in proportion to the oscillation cycle of the oscillating means, and can be switched to a predetermined delay amount by an external signal. Detection device. 30. The data detecting apparatus according to claim 27, wherein the delay amount of the delay unit is controlled in proportion to a current or voltage proportional to an oscillation cycle of the oscillating means, which is reduced and filtered. . 31. The phase comparison means provides a digital-analog converter that outputs a current or voltage proportional to the count value of the specific pattern width detection means, and a delay proportional to the output of the digital-analog converter. Comparing a phase difference between the output of the delay unit and the output of the pulse gate unit with the delay unit, the pulse gate unit that outputs the output clock edge information of the oscillation unit only when the binary signal is input, A phase difference detector that generates two pulses, which represent positive or negative depending on the sign of the phase difference, with a pulse width corresponding to the amount of phase difference, and detects the delay amount of the delay device by the specific pattern width detection. The data detection device according to claim 1, wherein the data detection device is controlled in proportion to the count value of the means.