KR19990048996A - Sampling clock regeneration circuit in optical disc reproducing apparatus employing P.M.L.detection method - Google Patents

Abstract

end. TECHNICAL FIELD This invention relates to an optical disc reproducing apparatus.

I. The technical problem to be solved by the invention: Sampling clock regeneration circuit that can reproduce the sampling clock in a wide range according to the double speed as well as DVD series and CD series in the optical disk reproducing apparatus adopting the PRML detection method to restore the data of the reproduction signal In providing.

All. Summary of the Invention Solution of the Invention: A converting means for converting and outputting an analog signal reproduced from an optical disk surface into a digital signal, and restoring predetermined data from a data stream output from said converting means. A sampling clock reproducing circuit of an optical disc reproducing apparatus employing an M. L method, comprising: a voltage controlled oscillator for oscillating and outputting a sampling clock frequency signal that is changed in proportion to an applied control voltage level, and A divider which divides at the division ratio corresponding to the type of optical disc being played and outputs it to the channel bit clock, and compares the maximum pulse width of the restored data with a reference range value set to correspond to the maximum pulse width inherent in the optical disk currently being reproduced. Channel frequency according to the frequency of the channel bit clock and the optical disc currently being reproduced. A first frequency error detection unit for detecting a frequency error between the first and second terminals and generating a frequency up / down control signal corresponding thereto and generating a lock signal when the channel bit clock is locked to the channel frequency; A phase detector which detects a phase difference between the digital signal output from the converting means and a zero crossing reference level, generates and outputs a first control voltage corresponding thereto, and generates a first control voltage corresponding to the frequency up / down control signal; And an adder for adding the second frequency error detector and the first and second control voltages to be applied to the voltage controlled oscillator.

la. Important use of the invention: It can be used for an optical disc player.

Description

Sampling clock regeneration circuit in optical disc reproducing apparatus employing P.M.L.detection method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical disk reproducing apparatus that employs a PRML detection method to restore recorded data. In particular, a sampling clock used for converting an analog signal reproduced from an optical disk surface into digital data is widely used according to a double speed mode. A circuit for reproducing.

A digital video disc (DVD) is one of optical recording media that can store an MPEG-2 digital image for more than two hours. Since these digital video discs and the known compact disc (CD) series are both optical, there are many similarities in the manner of recording and reproducing signals. As a result, a reproducing apparatus capable of selectively reproducing the DVD series and the CD series in one drive has emerged, and in such an optical disc reproducing apparatus, the data for accurately reproducing data recorded on various optical disc surfaces having different rotation speeds has been introduced. It is common to be provided with a phase locked loop circuit. On the other hand, in the optical disc reproducing apparatus employing the PRML method, a sampling clock signal necessary for A / D conversion of the analog signal reproduced through the optical pickup is provided from the phase locked loop circuit.

Hereinafter, the sampling clock reproduction process in the optical disc reproducing apparatus employing the PRML detection method will be described with reference to FIG. 1. First, FIG. It is shown. Referring to FIG. 1, the spindle motor 12 rotates in accordance with a drive control signal input from a motor driver to rotate the optical disk 10 mounted on the drive shaft at a fixed speed CLV or a right angle speed CAV. The optical pickup unit 14 optically picks up the data recorded on the surface of the optical disk 10, converts the data to an RF signal, which is an electrical signal, and outputs the RF signal to the RF amplifier 16. The optical pickup 14 is driven by a focus actuator for a focus servo and a tracking actuator for a tracking servo. The RF amplifier 16 amplifies and outputs an RF signal output from the optical pickup unit 14. The amplified analog RF signal is inputted to an analog-to-digital converter (ADC) 18 and sampled by a sampling clock SCLK output from the phase-locked loop 22 to perform a predetermined digital process through quantization and encoding. The data is converted into Ds and output. Thereafter, the digital data Ds is waveform-processed by the equalizer 20 and is shaped into a pulse waveform and output to the data detector. At this time, the phase synchronization loop circuit 22 obtains phase information of the channel bit clock at the edges of the digital data Ds pulses and synchronizes the phase of the sampling clock SCLK with the reproduction signal. However, since the phase synchronizing loop circuit 22 of the optical disc reproducing apparatus having the above-described structure is designed in a structure that can cope with a variable range of the narrow range channel bit clock frequency, it cannot be adapted to the multi-stage double speed mode. Will occur. In addition, the conventional optical disc reproducing apparatus employing the PRML detection method has a disadvantage in that it is difficult to integrate into a one-chip IC by using a plurality of phase-locked loops because the sampling clock regeneration circuit according to the double speed is used when reproducing the CD sequence.

Accordingly, an object of the present invention is to provide a sampling clock reproducing circuit capable of reproducing a sampling clock widely according to double speed as well as a combination of a DVD series and a CD series in an optical disc reproducing apparatus employing a PRML detection method to restore data of a reproduction signal. Is in.

It is still another object of the present invention to provide a sampling clock reproducing circuit that can access data at high speed even in an optical disc reproducing apparatus employing a PRML detection method to restore data of a reproduction signal.

According to an aspect of the present invention, there is provided a voltage controlled oscillator for oscillating and outputting a sampling clock frequency signal that varies in proportion to an applied control voltage level;

A divider for dividing the sampling clock frequency signal at a division ratio corresponding to the type of optical disc currently being reproduced and outputting the divided signal to a channel bit clock;

Detects the frequency error between the frequency of the channel bit clock and the channel frequency according to the optical disk currently being reproduced by comparing the maximum pulse width of the recovered data with a reference range value set to correspond to the maximum pulse width inherent in the optical disk currently being reproduced. And a frequency up / down control signal corresponding to the first frequency error detection unit for generating a lock signal when the channel bit clock is locked to the channel frequency.

A phase detection unit enabled by the lock signal and detecting a phase difference between the digital signal output from the converting means and the zero crossing reference level, and generating and outputting a first control voltage corresponding thereto;

A second frequency error detection unit generating and outputting a first control voltage corresponding to the frequency up / down control signal;

And an adder configured to add the first and second control voltages to the voltage controlled oscillator.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram of an optical disk reproducing apparatus that employs a Partial Response Signaling & Maximum Likelihood (PRML) detection scheme to restore data.

2 is a schematic block diagram of an optical disc reproducing apparatus having a sampling clock reproducing circuit 28 according to an embodiment of the present invention.

FIG. 3 is a detailed configuration diagram of the wide-range phase locked loop 24 of FIG. 2.

Hereinafter, the configuration and operation of a sampling clock regeneration circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a schematic block diagram of an optical disk reproducing apparatus having a sampling clock reproducing circuit 28 according to an embodiment of the present invention, and FIG. 3 is a wide-range phase locked loop of FIG. The detailed block diagram of (24) is shown. First, referring to FIG. 2, the reproduction signal picked up through the optical pickup unit 14 during the rotation of the spindle motor 12 is input to the RF amplifier 16 and amplified and output at a predetermined ratio. Is converted to. The digital data Ds are waveform-processed by the equalizer 20 and then input to the data detector 22 to restore desired data. On the other hand, the sampling clock regeneration circuit 28 according to the embodiment of the present invention is composed of a broad phase synchronous loop 24, a synchronization pattern, and a frequency error detection unit 26. As shown in FIG. 3, the wide-area phase-locked loop 24 further includes a phase detector including a phase comparator 30, a charge pump circuit 32, and a first LPF 34; 36) and a frequency error detection section composed of a second LPF 38, a VCO 42, and an adder 40. As shown in FIG.

Hereinafter, a sampling clock reproduction process according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3.

First, the VCO 42 of the wide-phase phase-locked loop 24 circuit oscillates the sampling clock frequency signal Fvco whose frequency and phase are varied corresponding to the level of the control voltage Vc applied from the adder 40. At this time, the free running frequency of the VCO 42 is set to a frequency from which the channel frequency used for the CD and the channel frequencies of the double speeds used for the DVD can be obtained. On the other hand, the sampling clock frequency signal Fvco is input to the synchronization pattern and the frequency error detection unit 26, and the sampling clock frequency signal Fvco input to the synchronization pattern and the frequency error detection unit 26 is divided and output to the channel bit clock by a divider. . The division ratio of the divider is set to a division ratio corresponding to the type of optical disc currently being reproduced. Meanwhile, the synchronization pattern and frequency error detection unit 26 compares the maximum pulse width of the restored data with a reference range value set corresponding to the inherent maximum pulse widths (CD; 11T, DVD; 14T) according to the optical disc currently being reproduced. The difference between the frequency of the channel bit clock and the channel frequency according to the optical disc currently being reproduced is detected. A frequency up / down control signal fu / fD for compensating for the detected error is generated and output to the wide-area phase locked loop 24. In addition, the synchronization pattern and frequency error detection unit 26 generates and outputs a lock signal when the channel bit clock is locked to the channel frequency. On the other hand, the frequency up / down control signal fu / fD output from the synchronization pattern and the frequency error detection unit 26 is applied to the charge pump circuit 36 in the wide range phase synchronization loop 24 circuit. Accordingly, the charge pump circuit 36 outputs a voltage level corresponding to the frequency up / down control signal fu / fD, and the output voltage is loop-filtered by the second LPF 38 to add to the second control voltage Vc2. Is applied.

On the other hand, the phase detector of the wide-area phase synchronization loop 24, which is composed of a phase comparator 30, a charge pump circuit 32, and a first LPF 34, is enabled by the lock signal and is output from the ADC 18. The phase difference between the digital signal and the zero crossing reference level is detected and a first control voltage corresponding thereto is generated and output. Specifically, first, the phase comparator 30 inputs a continuous data stream digitally converted by the ADC 18 of FIG. 2 to detect a phase error with a zero cross reference level, and corresponds to the detected phase error. It generates and outputs the phase error up / down control signal Up / Down. The phase error up / down control signal Up / Down generated as described above is applied to the charge pump circuit 32 so that the voltage level corresponding to the phase error up / down control signal Up / Down is increased in the charge pump circuit 32. The output voltage is loop-filtered by the first LPF 38 and applied to the adder 40 as the first control voltage Vc1. Therefore, the adder 40 generates the control voltage Vc applied to the VCO 42 by adding the first and second control voltages Vc1 and Vc2 output from the phase detector and the frequency error detector, respectively. Accordingly, the frequency and phase of the sampling clock frequency signal Fvco are variably adjusted in response to the control voltage Vc in the VCO 42 so that the sampling clock SCLK is a frequency corresponding to the speed of the optical disc type currently being reproduced and synchronized with the phase of the reproduction signal. Is generated.

As described above, the present invention has the advantage that the sampling clock can be reproduced widely according to the double speed as well as the DVD series and the CD series in the optical disc reproducing apparatus employing the PRML detection method.

Claims (2)

A converting means for converting and outputting an analog signal reproduced from the optical disk surface into a digital signal, and employing a P.M.L method for restoring predetermined data from the data stream outputted from the provided converting means. In the sampling clock reproducing circuit of the optical disc reproducing apparatus, A voltage controlled oscillator for oscillating and outputting a sampling clock frequency signal which varies in proportion to an applied control voltage level; A divider for dividing the sampling clock frequency signal at a division ratio corresponding to the type of optical disc currently being reproduced and outputting the divided signal to a channel bit clock; Detects the frequency error between the frequency of the channel bit clock and the channel frequency according to the optical disk currently being reproduced by comparing the maximum pulse width of the recovered data with a reference range value set to correspond to the maximum pulse width inherent in the optical disk currently being reproduced. And a frequency up / down control signal corresponding to the first frequency error detection unit for generating a lock signal when the channel bit clock is locked to the channel frequency. A phase detection unit enabled by the lock signal and detecting a phase difference between the digital signal output from the converting means and the zero crossing reference level, and generating and outputting a first control voltage corresponding thereto; A second frequency error detection unit generating and outputting a first control voltage corresponding to the frequency up / down control signal; And an adder configured to add the first and second control voltages to the voltage controlled oscillator. The method of claim 1, wherein the second frequency error detection unit comprises a charge pump circuit in which the output voltage is boosted and reduced by the frequency up / down control signal, and a loop filter for removing high frequency components of the output voltage. Sampling clock regeneration circuit characterized by.