JPS63285774A - Circuit for binarizing signal - Google Patents

Abstract

PURPOSE:To always a obtain a proper error signal and to set a slicing level at the optimum level, by controlling the slicing level by detecting the difference in phase between binarized signals and clocks. CONSTITUTION:When a slicing level is shifted considerably and the binarized signals and clocks do not synchronize to each other in phase, the interval between the rising edge of pulse signals from an inverting interval limiting circuit 7 and the edge of the binarized signals varies and the variation of the difference in pulse width between the output signal of a D-FF circuit 6 and the binarized signals is detected by means of a differential amplifier 5. When the inverting interval of the binarized signals is an integral multiple of the cycle of the clocks and, at the same time, the binarized signals are synchronous to the clocks, the pulse width from the inverting interval limiting circuit 7 is set shorter than the permissible inverting interval of the binarized signals when the slicing level becomes the optimum level by the cycle of the clocks and the variation of the slicing level is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal binarization circuit suitable for application to reproduction digital signals of optical disk devices.

[Conventional technology]

In optical disk devices, as a method of recording information signals,
As shown in FIG. 10(A), a device in which the length of a recording pit 101 is changed depending on the information content is known, and is used, for example, in a compact disc device. As shown in FIG. 10(B), the reproduced signal 102 has a smooth waveform that has been subjected to the band limitation of the reproduction system, so it is sliced at an appropriate slice level 103 and the waveform shown in FIG. 10(C) is obtained.
As shown in FIG. 2, it is necessary to convert the signal into a binary signal 104 having a length corresponding to the length of the pit. slice level 1
If 03 is set to the correct value, the binary signal 104
has a length that is exactly an integral multiple of the period T of the channel clock 105 shown in FIG.
In such a case, the resulting binary signal 104h has an error in the level inversion interval, as shown in FIG. 10(E).

In such a case, the phase of the edge of this binary high/high signal 104h and the corresponding clock 105h (Fig.
A phase shift E occurs between F) and F).
As described in Japanese Patent No. 9-152512, by detecting this phase error Eφ and performing negative feedback control on the slice level 103h, the optimum slice level 103 is always maintained.
It is possible to binarize the reproduced signal.

[Problem that the invention seeks to solve]

However, in the above conventional technology, FIG.
), when the deviation of the slice level 103g from the optimal slice level 103 becomes large, the resulting binary signal 10 shown in FIG. 11(B)
4g and the corresponding clock 105g (Figure 11 (C
)), in which case the feedback loop would be clocked in this state.

That is, the pit 1, which originally had a length of 4T, shown in FIG. 10(A)
01 is erroneously controlled by the slice level 103g as if a pit with a length of exactly 2T was detected.

As described above, the conventional technology that controls the slice level based only on the phase error has a problem in that the control loop has a plurality of stable points and is drawn into an incorrect slice level.

It is an object of the present invention to provide a signal binarization circuit that achieves this.

[Means for solving problems]

In order to achieve the above object, the present invention provides a first means for generating a clock from a binary signal obtained by slicing an input signal, and a first means for generating a clock from a binary signal obtained by slicing an input signal, and a first means for generating a clock from a binary signal obtained by slicing an input signal; a second means for generating a pulse signal having a rising edge and a pulse width of an integer of the period of the clock; a third means for latching the binarized signal with the pulse signal; and an output of the third means. a fourth means for generating a difference signal between the signal and the binarized signal, the slice level is controlled according to the difference signal, and the inversion interval of the binarized signal is within an allowable range. Set to the optimal level that is an integral multiple of the clock period.

[Effect]

If the slice level of the input signal deviates from the optimal level, the 2-bit signal obtained by slicing the input signal at the slice level
When the digitized signal is not synchronized with the clock, the interval between the rising edge of the pulse signal obtained from the second means and the edge of the binarized signal varies, and the output signal of the third means and the second Fluctuations occur in the difference in pulse width from the valued signal. The variation in this difference is detected by the fourth means, and by controlling the slice level with this, the slice level is set to the optimum level.

Also, the slice level is thicker than the optimal level (misalignment,
The inversion interval of the binarized signal is an integral multiple of the clock period and 2
When the digitized signal is synchronized with the clock, the above-mentioned effect of detecting the phase difference between the binarized signal and the clock cannot be used. Take advantage of the fact that there is a large difference in length.

That is, when either the high level period or the low level period becomes shorter than the pulse width of the pulse signal from the second means by more than a clock period, the leading edge of this short level period of the binarized signal and the pulse The phase relationship between the leading edge of the long level period and the rising edge of the pulse signal will be significantly different from the phase relationship with the rising edge of the signal.

For this reason, a difference in pulse width occurs between the binarized signal and the output signal of the third means, and by detecting this with the fourth means, fluctuations in the slice level can be detected. .

For this reason, if the pulse width of the pulse signal from the second means is set shorter by a clock period than the allowable inversion interval of the binarized signal when the slice level becomes the optimum level, the slice level Even if there is a large fluctuation in the slice level and the binarized signal is synchronized with the clock, this fluctuation in the slice level can be detected.

〔Example〕

An example of the information signal to which the present invention is applied is a reproduced signal from an optical disc.Here, the optical disc and its reproduced signal will be explained.

As shown in FIG. 4, the optical disc 21 has a holding hole 24 in its center, and its circumference is divided into 16 sectors. Each sector consists of preformat sections 2, 2 in which address information is recorded and a recording area 23 in which data is recorded. In such an optical disc 21, a preformat signal is initially recorded only in the preformat section 22, and no signal is recorded in the recording area 23, but by specifying a sector of a desired track, this sector can be read from the preformat signal. is detected, and a signal is recorded in the recording area 23.

FIG. 5 schematically represents a reproduced signal for one sector obtained from this optical disc 21, and 25 is a preformat signal reproduced from the preformat section 22 of the optical disc 21. Recorded in advance. 26 is the recording area 2 of the optical disc 21
3, there is a flag 26a at the beginning indicating that a signal is recorded in the sector, and after that, a VFO signal 26b for reproducing one clock is further reproduced by the width of the bell (i.e., the inversion interval). ) is the equal inversion signal of 4'T.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the signal binarization circuit according to the present invention, in which ■ is a comparison circuit, 2 is an approximately center detection circuit, 3 is a subtraction circuit, and 4 is a PLL (phase-locked circuit).
loop) circuit, 5 is a differential amplifier, 6 is a D-FF (D flip-flop) circuit, 7 is an inversion interval limiting circuit, 8 is an input terminal, 9 is an OR gate, 10 is a VFO detection circuit, 11
is an LPF (low pass filter). Further, FIGS. 2 and 3 are waveform diagrams showing signals of each part in FIG. 1, and signals corresponding to those in FIG. 1 are given the same symbols.

Here, first, it is assumed that the pulse inversion interval of the data 26c in FIG. 5 is limited to 3T to IIT.

Note that the VFO signal 26b is a repeating signal with a width of 4T, as described above.

First, a case where the slice level deviates slightly higher than the optimum level will be explained using FIG. 2.

Input signal A from input terminal 8 is sent to comparison circuit 1 and subtraction circuit 3
It is compared with the slice level ■ from , and becomes a binarized signal B. The PLL circuit 4 generates and outputs a clock C having a period T in synchronization with this binary signal B. The binary signal B is also supplied to the VFO detection circuit 10, and the detection signal ■ is "H" (high level) when the VFO signal 26b is detected, and "L" (low level) when it is not detected.
is output. The inversion interval limiting circuit 7 receives the binary signals B, V
The detection signal I and clock C of the FO detection circuit 10 are supplied, and a 3T limit signal and a 4T limit signal E are generated and output. The 3T limit signal rises at the first rising edge of clock C after each edge of binary signal B, and has a width of 2T.
The 4T limit signal E is the “H” signal of the detection signal I.
When it is “L”, it is “L”, but when it is “H”, it is “H” with a width of 3T rising in synchronization with the 3T limit signal.
This is the signal. The OR gate 9 outputs a sampling clock F which is the logical sum of the clock C, the 3T limit pulse D, and the 4T limit pulse E.

This extracted clock F is 2 times from the edge of the binary signal B.
The waveform is obtained by removing the clock for a period of D-
It is input to the CK terminal of the FF circuit 6, and the binary signal B is latched at its rising edge.

This output signal is input to the child terminal of the hyN differential amplifier 5. Further, one terminal of this differential amplifier 5 is connected to a binary signal B.
is input directly. The differential amplifier 5 outputs a difference signal H, which is a bipolar pulse. The width of the positive part of this difference signal H changes according to the slice level error, and when the slice level ■ is higher than the optimal level ■ o, the next width becomes wider by Eh (therefore, the DC When the component is extracted by the LPFll, this DC component becomes a slice level error signal HD representing the difference between the slice level (2) and the optimum level (2).

On the other hand, the input signal A is also supplied to a substantially center detection circuit 2, and a signal representing the substantially center level of the input signal A is output. The slice level error signal H from LPFil is subtracted from this signal by the subtracting circuit 3, and the slice level ■ is set.

FIG. 2 shows a portion of data 26C (FIG. 5), and at this time, the detection signal I from the VFO detection circuit 10 is "L" and the 4T limit pulse E is also "L".

Therefore, a composite pulse of the clock C and the 3T limited pulse D is obtained as the output signal F from the OR gate 9.

Furthermore, FIG. 2 shows a case where a phase difference of T/2 occurs between the binarized signal B and the clock C, and the rising edge of the binarized signal B is the falling edge of the clock C. If they match, the next falling edge of binarized signal B matches the rising edge of clock C, and furthermore, the next rising edge of binarized signal B matches the falling edge of clock C. .

In such a case, every other rising edge of the 3T limited pulse D lags the rising edge of the binary signal B by T/2, and the other every other rising edge lags the falling edge of the binary signal B. T is behind Edge. 3T limit pulse D H
” has a time width of 2T, its falling edge coincides with the rising edge of clock C, and the 3T limit pulse D
The period from the falling edge to the next rising edge (ie, the "L" period) is an integer multiple of T. Therefore, if n is an integer greater than or equal to 1, the output signal F of the OR gate 9 is such that the falling edge of the 3T limit pulse D is delayed by T/2 by the clock C, and the "L" period is T/2. The length of the odd-numbered pulse is 2n+1)T/2.
``This is a signal in which n clocks C are inserted at equal intervals during the period.

Therefore, when the D-FF circuit 6 latches the binary signal B at the rising edge of the output signal F of the OR gate 9, the D-FF circuit 6 outputs a signal G whose inversion interval is an integral multiple of T. can get. Since the rising edge of this signal G lags behind the rising edge of the binary signal B by T/2,
When the binary signal B is subtracted from the signal G by the differential amplifier 5,
A difference signal H falls at the rising edge of the binary signal B and has a negative polarity portion with a width of T/2, and a difference signal H rises at the falling edge of the binary signal B and has a positive polarity portion with a width of T. can get. Therefore, a slice level error signal HIll having a level corresponding to the difference in time width between the positive polarity portion and the negative polarity portion is obtained from LPFII.

This slice level error signal HI) corresponds to the phase difference between the binarized signal B and the clock C, and is
and clock C are in phase synchronization, the difference signal H
The time widths of the positive and negative polarity portions become equal, and the slice level error signal Ho becomes zero. Also, the slice level ■ is the optimal level ■.

When the time width of the negative polarity portion of the difference signal H is longer than the time width of the positive polarity portion, the slice level error signal HD becomes negative.Therefore, the approximately center detection circuit 2
By subtracting the output signal of , by the slice level error signal H, the slice level ■ is set to the optimum level v0.

Next, the slice level V is the optimal level ■. The case where there is a large deviation from the VFO signal will be explained using FIG. 3, including the VFO signal part.

In this case, as explained earlier, the binarized signal B and the clock C may be synchronized, but the FO signal 26
b is used to detect a large deviation in the slice level ■. In this VFO signal 26b, the VFO detection circuit 10
The output signal ■ becomes "H". Therefore, the inversion interval limiting circuit 7 outputs the 4T limiting pulse Et+ together with the 3T limiting pulse D.

The 4T limit pulse E rises at the rising edge of the clock C after each edge of the binarized signal B, and is a 3T wide "H" signal. However, if the falling edge of the 4T limit pulse E exceeds the falling edge of the binarized signal B, the next rising edge of the 4T limit pulse E will be the rising edge of the clock C after the previous falling edge. Matches Edge. Therefore, the "H" period of the 3T limit pulse D is included within the "H" period of the 4T limit pulse E. Therefore, the clock F extracted from the OR gate 9 becomes a composite signal of the 4T limit pulse E and the clock C during the period of the VFO signal 26b.

When the slice level ■ becomes sufficiently higher than the optimum level v0, the "L" period of the binary signal B becomes longer than the "H" period. Since the binarized signal B is phase-synchronized with the clock C, here, in the VFO signal 26b, the "H" period of the binarized signal B is assumed to be 3T, and the "L" period is assumed to be 5T (
That is, the period of the VFO signal 26b is 8T).

For such a binary signal B, the 4T limit pulse E rises at the first rising edge of the clock C after the rising edge of the binary signal B, but at the next falling edge of the 4T limit pulse E. The edge is T than the falling edge of the binary signal B.
/2 (=, 3T-(3T+T/2)), the rising edge of the 4T limit pulse E following this falling edge is 3T/
Late by 2. In other words, every other rising edge of the 4T limit pulse E is T/
However, every other rising edge lags behind the falling edge of the binary signal B by 372T. Further, the interval from the falling edge to the rising edge of the 4T limit pulse E is T.

Therefore, the extracted clock F from the OR gate 9 corresponds to the 4T limit pulse E extended by T/straddling the falling edge side.

In the D-FF circuit 6, when the binary signal B is latched by the sampling clock F, the rising edge of the output signal G is delayed by T/2 from the rising edge of the binary signal B, and the falling edge is a binary signal. The signal is delayed by 3T/2 from the falling edge of the conversion signal B. Therefore, by subtracting the binarized signal B from this signal G, a difference signal H is obtained in which negative polarity portions having a width of T/2 and positive polarity portions having a width of 3T/2 are alternately arranged. Therefore, a positive slice level error signal Ha is obtained from the LPF 11. This results in
The slice level V is lowered.

Then, the phases of the binarized signal B and the clock C become shifted, and the operation shown in FIG. 2 is performed, and the slice level V
is further reduced.

When slice level V is equal to optimal level v0,
The 'H'' and IIL'' periods of the VFO signal 26b are both 4T.
Therefore, the periods of the negative polarity portion and the positive polarity portion of the difference signal H become equal, and the slice level error signal H becomes zero.

Also, the slice level ■ is the highest level ■. , the binary signal B from the VFO signal 26b is “H”
The period becomes longer than the "L" period, and the slice level error signal He becomes negative. Therefore, in any case, the slice level ■ is set to the optimum level v0.

In this way, even if the slice level V deviates sufficiently from the optimum level v0 and the binarized signal B is phase synchronized with the clock C, it becomes "H" every 4T period.

By using the VFO signal 26b which should be repeated as "L", the slice level 2 is detected and shifted to the optimum level. Along with this, the VFO signal 26b
The binary signal B from is "11".

“L” period becomes 4T, and along with this, data 2
6c is also 3T or more. In this way, the reversal interval is 3
Limited to T or more.

FIG. 6 is a circuit diagram showing an example of the approximate center detection circuit 2 in FIG. 1. In the figure, a human power signal A, which is input to the input terminal 8 of FIG. 1, is input from an input terminal 102. As shown in FIG.
A positive envelope line 102p of is detected. Moreover, this input signal A is connected to negative resistors 2g, 2i, 21. As shown in FIG. 7, a negative envelope 102n of the input signal A is detected by a negative envelope detection circuit including a capacitor 2j and transistors 2h and 2k. These positive and negative envelope signals are divided by a voltage dividing resistor 2m, and approximately the center level of the input signal A is outputted to the output terminal 102S.

FIG. 8 is a block diagram showing a specific example of the inversion interval limiting circuit 7 in FIG. 1.゛In the same figure, input terminal 1
04 is the binary signal B, the input terminal 112 is the output signal ■ of the VFO detection circuit 10 (Fig. 1), and the input terminal 109 is
are supplied with a clock C, respectively. D-FF circuit? a,
7b, 7c, and 7d are connected in series, the binary signal B becomes the D input of the first stage D-FF 7a, and the clock C is connected to each D-FF.
The clock is manually clocked for F7a to 7d.

Therefore, when the binary signal B becomes "H", the D-FFs 7a, 7
Their Q outputs become “H” in the order of b, 7c, and 7d,
When the binary signal B becomes “L”, the clock C
D-FF7a, 7b, 7c, 7 sequentially at each rising edge of
Their Q outputs become "L" in the order of d. therefore,
D-FF circuit? Ex-O to which the Q outputs of a and 7c are supplied
The signal from the R gate 7e rises at the first rising edge of the clock C after each edge of the binarized signal B and has a width of 2f.
A T-limited pulse D is obtained, and from the Ex-OR gate 7f, a 4T-limited pulse E which rises at the first rising edge of the clock C after each edge of the 2(! ratio signal B and is 3f wide) is obtained.
is obtained. This 4T limit pulse E is outputted via the AND gate 7g when the output signal I of the VFO detection circuit 10 is "H".

FIG. 9 is a block diagram showing an example of the VFO detection circuit 10 in FIG. 1. In the figure, first, the flag detector 10a detects the flag signal 25a (fifth
) is detected, and using the signal as a trigger, the mono multi-circuit 10b receives the detection signal I for a predetermined period of time, and the inversion interval limiting circuit 7
Output to.

In the above explanation, when the slice level is largely shifted and the binarized signal is synchronized with the clock, it is referred to as VF.
Although the detection is performed during the period of the O signal, it is similarly detected during the period of the shortest inversion interval of 3T during the data period. However, in the data period, the inversion period is 3T to 1
It can change between 1T, and even if the slice level deviates significantly, the inversion period will be shorter than 3T for an irregular period of time. From this, there is a meaning in detecting the above state during the period of the FO signal whose inversion interval is constant.

The embodiments of the present invention have been described above with respect to a signal having a VFO signal whose inversion interval changes in the range of 3T to 11T and a constant inversion interval of 4T. It's okay. Also, D-F in Figure 1
It goes without saying that the method of limiting the inversion interval of the output of F6 is not limited to the method of extracting the clock as described above, but other methods may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, even when the slice level is largely shifted and the binarized signal and the clock are phase-synchronized, even when this cannot be detected.
．． A correct error signal can always be obtained, and the slice level can be accurately controlled to the lowest level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a signal binarization circuit according to the present invention, and FIGS. 2 and 3 are waveform diagrams showing signals in each part of FIG. 1 for different amounts of variation in the slice level, respectively. Figure 4 is a plan view of the optical disc, and Figure 5 is 1 of Figure 4.
FIG. 6 is a circuit diagram showing a specific example of the approximate center detection circuit in FIG. 1, FIG. 7 is an explanatory diagram of its operation, and FIG. 8 is an inversion interval in FIG. 1. 9 is a block diagram showing a specific example of the limiting circuit; FIG. 9 is a block diagram showing a specific example of the VFO detection circuit in FIG.
0 and 11 are signal waveform diagrams showing the operation of a conventional signal binarization circuit, respectively. 1.-----Comparison circuit, 2---Approximate center detection circuit, 3--.Subtraction circuit, 4-----P L L circuit, 5------1. -Differential amplifier, 6・-・-%[)
Flip-flop, 7.----inversion interval limiting circuit,
a--1--input terminal, 9--OR gate,
10--------V FO detection circuit, 11-...-
L.P.F. Agent Patent Attorney Takeshi Kenjibe (1 other person) Figure 1 Figure 2 Kuno (J O-LLIL Q Engineering Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10) Figure 11

Claims (1)

[Claims] 1. In a signal binarization circuit configured to obtain a binarized signal by slicing an input signal, a first means for generating a clock from the binarized signal; a second means for generating a pulse signal that rises in synchronization with the clock for each edge of the signal and has a pulse width that is an integral multiple of the period of the clock; and a third means that latches the binarized signal with the pulse signal. and a fourth means for generating a difference signal between the output signal of the third means and the binarized signal, controlling the slice level of the input signal according to the difference signal, and controlling the slice level of the input signal according to the difference signal. A signal binarization circuit characterized in that the inversion interval of the binarized signal is set to an optimum level that is an integral multiple of the period of the clock within a permissible range. 2. In claim 1, the binarized signal has an equal duty ratio section in which an inversion interval is constant when the slice level reaches the optimum level, and the second means generates The pulse signal has the same duty ratio interval as the first pulse signal whose pulse width is shorter than the shortest inversion interval within the preset range of the optimal level by the period of the clock. The second pulse width is shorter than the inversion interval by the period of the clock.
, wherein the latch signal of the third means is the first pulse signal outside the equal duty ratio interval and the second pulse signal during the equal duty ratio interval. Signal binarization circuit.