JPH08180588A - Reproduced data extracting apparatus - Google Patents

Abstract

PURPOSE: To enlarge a detection window margin with a simplified structure, on the occasion of extracting reproduced data including a DC element, by controlling the reference level of a level comparison circuit with error signal from a phase difference detecting circuit. CONSTITUTION: A comparator 31 as a level comparison circuit slices the reproduced data with a predetermined reference level to obtain a digital signal. A phase comparison circuit 45 synchronizes the phase of clock signal generated by PLL44 with any one S42 of the rising or falling edge of the pulse signal S31 outputted from the comparator 31. Moreover, this circuit also detects a phase difference between the output signal S44 of PLL44 and the other S43 of the rising or falling edge of the output signal 531 of the circuit 31. An adder circuit 36 adds an error signal S45 depending on the phase error to the slice level for comparison in the comparator 31. With this structure, even when an original data is recorded in the asymmetry condition, the reference level of the comparator 31 is controlled to compensate for the asymmetry condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduction data extracting device for accurately extracting data from a reproduction signal when reproducing data recorded by, for example, a pit edge recording system.

[0002]

2. Description of the Related Art Generally, when recording an optical disk,
By heating the recording medium with the energy of the laser light beam, its optical or magneto-optical property is changed to record data.

Then, in the pit edge recording system in which the inversion interval of the recording signal and the edge of the pit are made to correspond to each other, ideally, as shown in FIG. Pits are formed such that the edges are at predetermined positions.

However, in actuality, due to the thermal characteristics of the optical disk such as the thermal diffusion of the recording layer, FIG.
As shown in C, the leading edge and the trailing edge of the pit shift from the predetermined position to the front and the rear, respectively, and the pit is formed in a so-called asymmetry state.

In the case of an ideal pit train as shown in FIG. 6B, the reproduction signal from the optical pickup is schematically shown in FIG.
On the other hand, in the case of the asymmetric pit train as shown in FIGS. 6A and 6C, the reproduced signal becomes as shown in FIGS. 6D and 6F, respectively.

When these reproduction signals are extracted (sliced) at a predetermined level, reproduction data (hereinafter referred to as reproduction pulse train) corresponding to an ideal pit train becomes as shown in FIG. 6H. On the other hand, the reproduction pulse trains corresponding to the pit train in the asymmetry state are as shown in FIGS. 6G and 6G, respectively, and the changes in the positions of the leading edge and the trailing edge of the pits are the same as the time of the leading edge and the trailing edge of the reproducing pulse. Appears as a transition.

The window margin for reproducing the binary data of "1" and "0" from the reproduction pulse train is
Since the reproduction pulse train from an ideal pit train as shown in FIG. 6H is set with a margin of a predetermined width, in the reproduction pulse train corresponding to the pit train in the asymmetry state as shown in FIGS. 6G and J, The window margin is reduced by the amount of transition of the leading edge and the trailing edge of the pulse, which leads to deterioration of the error rate.

As a method for solving the above-mentioned problem caused by the asymmetry-state pit train, the conventional method shown in FIG.
It is well known to apply negative feedback to the extraction circuit, as shown in FIG.

In FIG. 7, reference numeral 10 denotes a negative feedback type extraction circuit, which reproduces a reproduction signal Spb from its input terminal 10i.
(See FIGS. 6D to 6F described above) is supplied to the non-inverting input terminal of the comparator (level comparison circuit) 11. A reproduction pulse train as shown in FIGS. 6G to 6J is generated at the output terminal of the comparator 11 and is led to the output terminal 10d. At the same time, the inverting input terminal of the comparator 11 is passed through the low-pass filter 12 and the amplifier 13. Be negatively fed back to.

When the original recording data has the same "H" period and "L" period and no direct current component, even if the pit train on the optical disk is formed in the asymmetry state, this asymmetry state is generated. The DC component generated in the reproduction pulse train is canceled by the above-mentioned negative feedback, and a reproduction pulse train similar to the original recording data, which has no DC component, is obtained at the output terminal of the comparator 11.

[0011]

However, the negative feedback type extraction circuit as shown in FIG. 7 is effective only when the original recording data does not have a DC component, that is, when it is so-called DC-free. When the original recording data is not DC-free like the variable length code, it was not possible to compensate the asymmetry state of the pit as described above.

Even if the original recorded data is not DC-free, a method for compensating for the asymmetry state of the pits described above is, for example, the separation edge detection at the 1990 Autumn National Convention of the Institute of Electronics, Information and Communication Engineers. A scheme has been proposed.

In this separated edge detection method, the leading edge and the trailing edge of the reproduction pulse are separated and detected to form the leading edge pulse and the trailing edge pulse.
Data can be combined by a circuit as shown in FIG. 1 and input to a normal demodulator.

In FIG. 8, 21LD and 21TR are shown.
Is the leading edge pulse PLD and trailing edge pulse PTR as described above.
The edge data detection circuits respectively correspond to.

In the one edge data detection circuit 21LD, the leading edge pulse PLD is supplied to the PLL (Phase Locked Loop) 22LD and the synchronization mark detection circuit 23LD, and the leading edge pulse PLD and the clock generated in the PLL 22LD are supplied. It is supplied to the data detection circuit 24LD,
Binarized data corresponding to the leading edge pulse PLD is detected.
The binarized data is sequentially supplied to a FIFO (First In First Out) memory 25LD according to a clock from the reference clock generation circuit 26.

When the sync mark detecting circuit 23LD detects the sync mark in the reproduced data, the storage number of the sync mark corresponding data in the data stored in the FIFO memory 25LD can be known for each edge data. Then, based on this number, the data is sequentially taken into another memory from the head address of the data.

The trailing edge pulse PTR is also supplied to the other edge data detection circuit 21TR having the same configuration as described above, and the same processing as described above is performed.

Both edge data detection circuits 21LD and 21T
The binarized data as described above is read from each of the R FIFO memories 25LD and 25TR by using the reference clock of the generation circuit 26, and the data synthesis circuit 27 sequentially obtains a logical sum to obtain a series of data. A data string is obtained and input to the normal data demodulation circuit 28.

In the separated edge detecting method as described above, F
The IFO memory absorbs the asymmetry state of the pits as described above, so that the detection window width can be effectively widened and the allowable value of the variation of the optical disc and the recording / reproducing apparatus can be enlarged.

However, the above-mentioned separated edge detection method has a problem that a pair of PLLs respectively corresponding to the leading edge and the trailing edge of the reproduction pulse are required, which complicates the configuration.

In view of the above point, an object of the present invention is to increase the detection window margin and to reduce the error with respect to the reproduced data including a DC component and a code capable of self-clocking with a relatively simple structure. An object is to provide a reproduction data extraction device capable of reducing the rate.

[0022]

In order to solve the above-mentioned problems, the reproducing data extracting device according to the present invention, when the reference numerals of the embodiments described later are made to correspond to the codes including a DC component and capable of self-clocking. And a level comparison circuit 31 for slicing the reproduction data into a binary value by slicing the reproduction data with a predetermined reference level, and a clock signal for the reproduction data that is phase-locked with one of the rising and falling S42 of the output signal S31 of the level comparison circuit 31. And a clock signal S4 from the phase synchronization circuit 44
4 and an error signal S45 corresponding to the phase difference between the output signal of the level comparison circuit 31 and the other rising or falling S43 of the output signal of the level comparison circuit 31, and the level comparison circuit 31. And an adder circuit 36 for adding to the slice level for comparison.

[0023]

With this configuration, even when the original data is recorded in the asymmetry state, the output signal S of the level comparison circuit 31 is generated by the error signal S45 from the phase difference detection circuit 45.
The rising S42 and the falling S43 of 31 are PLL4
The reference level of the level comparison circuit 31 is controlled so as to be synchronized with the phase of the reproduction clock S44 of No. 4, and the asymmetry state at the time of recording the original data is corrected.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a reproduction data extracting device according to the present invention will be described below with reference to FIGS.

[Structure of Embodiment] FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, reference numeral 30 designates an extraction circuit as a whole, and a reproduction signal S from its input terminal 30i.
pb is supplied to the non-inverting input terminal of the comparator (level comparison circuit) 31 and the positive envelope detection circuit 32
And the negative envelope detection circuit 33 are commonly supplied.
Output signals S32 and S of both envelope detection circuits 32 and 33
33 is supplied to the averaging circuit 34, from which the average value of both output signals S32 and S33 ((S32 + S33) / 2)
Is obtained. The output signal S of this averaging circuit 34
34 is supplied to the inverting input terminal of the comparator 31 through the low-pass filter 35 and the adder circuit 36.

The output signal S31 of the comparator 31 is D
It is supplied to the data input terminal of the type flip-flop circuit 41 and is commonly supplied to the rising edge detection circuit 42 and the falling edge detection circuit 43. The output signal S42 of the rising edge detection circuit 42 is supplied to the PLL 44. The PLL 44 outputs a clock S44 that is in phase with the output signal S42. The clock S44 and the output signal S43 of the fall detection circuit 43 are supplied to the phase comparison circuit 45.

The output signal S45 of the phase comparison circuit 45 is supplied to the addition circuit 36 through the low-pass filter 46, the addition circuit 47, and the amplifier 48. Then, the output data D41 of the D-type flip-flop circuit 41 is output to the output terminal 30d.
And the recovered clock S from the PLL 44.
44 is led to the output terminal 30ck.

Further, the output signal S31 of the comparator 31
However, the resync detection circuit 51 and the run length determination circuit 52
And the reproduction clock S from the PLL 44.
44 is supplied to the resync detection circuit 51, and the output signal S51 of the resync detection circuit 51 is supplied to the run length determination circuit 52.

The run-length judging circuit 52 includes a judging clock S5 having a frequency from the clock generating circuit 53 which is a predetermined integral multiple of the reproduction clock frequency f44 of the PLL 44.
3 is also supplied, and the output signal S of the run length determination circuit 52
52 is supplied to the voltage generation circuit 54, and the voltage generation circuit 54
The output signal S54 of is supplied to the adder circuit 47 through the low-pass filter 55.

[Processing Target Data] Next, the processing target data according to the embodiment of the present invention will be described with reference to FIG.

In the embodiment shown in FIG. 1, write once
Once type and rewritable magneto-optical (Magneto-Optical
The data recorded in the sector format as shown in FIG. 2 is processed on the) type optical disc.

An appropriate variable length code, for example, (1-7) run length limited code is used for recording data on the disc.
The (1-7) RLL code is a code in which "1" is inserted between "1" and "1" at a minimum of 1 to a maximum of 7, and a predetermined encoder Therefore, for example, 8
Converted from bit data.

When NRZI is used as the modulation method of the recording data, "1" is the inversion of the recording signal and "0".
Becomes non-inverted, so by using the RLL code,
The inversion interval can be opened, and the transmission band can be narrowed.

As shown in FIG. 2A, each sector of the disk is composed of a preformat (prepit) area and a data area. The preformat area is provided with each area as shown in FIG. 2B. Are provided with respective regions as shown in FIG. 2C.

In the pre-formatted area, the VF for pulling in the PLL in advance following the first sector mark SM
O (Variable Freqency Oscilator), address mark AM, and identification data ID (ID
entifier) is repeated twice, for example, and then a postamble PA and a blank portion GAP are provided.

The sector mark SM needs to be easily extracted, is not based on the rule of the above (1-7) RLL code, and is DC-free, for example, 5
Between each "1", 5, 11, 11, 5
A specific data pattern is used such that "0" s are inserted.

For VFO, a DC-free data pattern such as "010101010101" is used in the shortest cycle. The address mark AM includes (1-
7) A unique data pattern such as "0000000010" that is not based on the rule of the RLL code and is not DC-free is used.

In the ID area, track numbers and sector numbers are pre-formatted according to the rule of (1-7) RLL code. The postamble PA has the above-mentioned V
A DC-free data pattern similar to FO, such as “01010101 ... 01”, is used.

In the data area, the same VF as above is used.
After O and the synchronization signal SYNC, for example, 32 bytes of data DATA and 1 to 2 bytes of resync RESY
After NC and NC are repeated multiple times, the error correction code ECC
Is provided, and the blank part GAP is provided after the data DATA to the error correction code ECC are repeated a plurality of times.

In this embodiment, as described above, the data D
ATA is a (1-7) RLL code, not DC-free. The error correction code ECC is also (1-7) RLL.
Code, not DC-free.

The resync RESYNC is a signal for resynchronization that is inserted to prevent the propagation of an error when there is a defect in the data, and DC-free is desirable,
A fixed pattern of known length, eg "10000000
The longest pattern of the (1-7) RLL code such as "10000001" is used.

[Operation of Embodiment] Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

In the embodiment of FIG. 1, first, the low pass filter 3
In the output signal S35 of No. 5, using the portion corresponding to the DC-free pattern of the preformatted area as described above,
The slice level at the inverting input terminal of the comparator 31 is roughly set. Next, the output signal S46 of the low-pass filter 46 is added to finely set the slice level of the comparator 31. Then, the output signal S55 of the low-pass filter 55 is added to correct the slice level of the comparator 31.

[Setting of Slice Level] Envelope detection circuit 3 in which the reproduction signal Spb as shown in FIG. 3A has positive and negative sides.
2 and 33, both envelope detection circuits 32 and 33
From the output signal S as shown in FIGS. 3B and 3C, respectively.
32 and S33 are obtained. The output signals S32 and S33 of the envelope detection circuits 32 and 33 are averaged in the averaging circuit 34, and as shown in FIG.
34, the level of the portion corresponding to the DC-free pattern in the reproduction signal Spb becomes zero V.

The output signal S34 of the averaging circuit 34 is supplied to the low-pass filter 35, and as shown in FIG. 3E, the output signal S35 of the low-pass filter 35 from which the high-pass components have been removed is output from the inverting input terminal of the comparator 31. The slice level of the comparator 31 is coarsely set by the zero V level portion corresponding to the DC free pattern in the reproduction signal Spb as described above.

The output signal S35 of the low pass filter 35
Of these, a portion corresponding to the DC-free pattern may be sample-held.

On the other hand, in the portion corresponding to the non-DC-free data pattern in the reproduction signal Spb, the comparator 3
The output signal S31 of 1 becomes, for example, as shown in FIG. 4A. In FIG. 4A, when the reproduction signal Spb corresponds to an ideal pit row, it is shown by a solid line, and when the reproduction signal Spb corresponds to the pit row in the asymmetry state, it is shown by a dotted line and a broken line, respectively. .

The output signal S of such a comparator 31
31 is a rising and falling detection circuit 42, 4
4B from the rising edge detection circuit 42.
The output signal S42 as shown in FIG. 4 is obtained, and the output signal S43 as shown in FIG. 4C is obtained from the fall detection circuit 43. Also in FIG. 4C, the output signal S43 when the reproduced signal Spb corresponds to an ideal pit string is shown by a solid line, and the output signal S43 when the reproduced signal Spb corresponds to a pit string in an asymmetric state is a dotted line, respectively. It is indicated by a broken line and.

When the output signal S42 of the rising edge detection circuit 42 as shown in FIG. 4B is supplied to the PLL 44, the PLL 4
4 operates in phase with the output signal S42 of the rising edge detection circuit 42, and the reproduction clock S44 as shown in FIG. 4D is obtained from the PLL 44. In this embodiment, the frequency f44 of the PLL 44 is set to a predetermined integer multiple of the data frequency.

When the reproduction clock S44 and the output signal S43 of the falling edge detection circuit 43 are supplied to the phase comparison circuit 45, if the reproduced signal Spb corresponds to an ideal pit train, the falling edge detection circuit. Since there is no phase difference between the output signal S43 of S43 and the reproduced clock S44, the output signal S45 of the phase comparison circuit 45 becomes zero V as shown in the intermediate portion of FIG. 4E.

Further, when the reproduction signal Spb corresponds to the pit train in the asymmetry state, the phase of the output signal S43 of the falling detection circuit 43 is delayed or advanced with respect to the reproduction clock S44. The output signal S45 of S.45 is signal S, as shown in the upper and lower sides of FIG. 4E.
The signal becomes a signal corresponding to a positive or negative pulse train corresponding to the delay or advance of the phase of 43, respectively.

The output signal S of the phase comparison circuit 45 as described above.
When 45 is supplied to the low-pass filter 46, the reproduction signal Spb
Corresponds to the pit row in the asymmetry state, the phase error signal S46 from which the high frequency component is removed is obtained as shown in the upper side and the lower side of FIG. 4F.

Then, the phase error signal S46 is appropriately amplified by the amplifier 48 and is negatively fed back to the inverting input terminal of the comparator 31 to control the slice level, so that finally, the intermediate portion of FIG. 4F is obtained. As shown in
The phase error signal S46 is set to zero V.

In other words, even when the reproduction signal Spb corresponds to the pit train in the asymmetry state, the rising and falling edges of the output signal S31 of the comparator 31 are
The asymmetry state of the pit train as described above is corrected in synchronization with the phase of the reproduction clock S44 of the PLL 44. As a result, the reproduction data detection window margin is expanded, and the error rate is reduced.

The output signal S31 of the comparator 31
Rising and falling detection circuits 42 and 43
, And the relationship between the PLL 44 and the phase comparison circuit 45 can be reversed from that in the embodiment of FIG.

[Correction of slice level] As described above,
Since the frequency f44 of the clock S44 from the PLL 44 is set to a predetermined integer multiple of the data frequency, the PLL 44 may be phase locked to the data with an integer ratio different from the setting.

In this case, the output signal S of the comparator 31
The falling edge of 31 is 1 of the output clock cycle of the PLL 44.
If it deviates by more than / 2, the path to the inverting input terminal of the comparator 31 becomes positive feedback through the phase comparison circuit 45, and as a result, 1T (T is one data cycle corresponds to one cycle of the output clock S44 of the PLL 44). ) Where there is a shift,
The slice level may be set. For example,
Data such as “101000010001” becomes “11
"0000001010" and "100100010000
There is a possibility that erroneous asymmetry correction will be performed as in "01".

Therefore, in this embodiment, a positive feedback state is prevented by checking the set slice level using a signal having a known pattern and a high appearance frequency. As the signal for this check, the above-mentioned resync signal is used in this embodiment.

In the case of (1-7) RLL code, the pattern of the resync signal is, for example, "10" as shown in FIG. 5A.
00000010000001 ", and the waveform of the portion corresponding to the resync signal in the output signal S31 of the comparator 31 is as shown in FIG. 5B.

This resync signal is supplied to the resync detection circuit 5
1 is detected by pattern matching in FIG.
The detection signal S51 as shown in C is supplied to the run length determination circuit 52.

In the determination circuit 52, in the signal S31 from the comparator 31, as shown in FIG. 5B, a period T1 of "H" and a period T of "L" of the waveform corresponding to the resync signal.
2 is measured by using the determination clock S53 from the clock generation circuit 53 as shown in FIG. 5D, it is determined whether the slice level setting of the comparator 31 is correct or deviated. It

The "H" period T1 and the "L" period T2 of the resync signal corresponding waveform shown in FIG.
It is known that the data period is 7 data periods and the difference between the two is 1 data period.

In this embodiment, the frequency of the determination clock S53 is set to, for example, 10 times the frequency of the output clock S44 of the PLL 44, and thus the frequency of the period T1 and T2 of FIG. The wave numbers N1 and N2 of the determination clock S53 are, for example, 80
And 70, and the difference between the two becomes 10 waves.

When the slice level of the comparator 31 is set correctly and the falling edge of the waveform corresponding to the resync signal in FIG. 5B is at the correct position, the error signal S52 output from the determination circuit 52 is [0].

The falling clock is 1 / of the clock cycle
If the trailing edge of the waveform corresponding to the resync signal in FIG. 5B advances by 2 by ½ of the data cycle from the correct position, the wave numbers N1 and N of the determination clock S53 in FIG. 5D are advanced.
2 becomes 75 in all cases. In this case, the determination circuit 52 outputs the error signal S52 of [-10].

When the falling clock is delayed by 1/2 of the clock cycle and the falling edge of the waveform corresponding to the resync signal of FIG. 5B is delayed by 1/2 of the data cycle from the correct position, the determination of FIG. 5D is made. Wave number N for clock S53
1 and N2 become 85 and 75, respectively, and the determination circuit 52
Outputs an error signal S52 of [+10].

The error signal S52 from the determination circuit 52 as described above is converted into the corresponding analog voltage S54 in the voltage generation circuit 54, supplied to the adder 47 through the low pass filter 55, and then the low pass filter. It is added to the asymmetry correction signal S46 from 46, and the slice level setting of the comparator 31 is corrected.

In this embodiment, the low pass filter 5
The time constant of the low-pass filter 46 is set smaller by, for example, about one digit than the time constant of 5, and the fall detection circuit 43 is set.
The asymmetry correction loop including the phase comparison circuit 45 and the phase comparison circuit 45 responds promptly.

Instead of the low pass filter 55, the input signal S54 may be sampled and held. Further, instead of the determination clock S53, the PLL 44
It is also possible to appropriately use the reproduced clock S44 from FIG. 1 by multiplying the frequency, but in this embodiment, a separate clock generation circuit 53 is provided in order to avoid runaway.

Further, instead of the resync signal, a VFO signal or a SYNC signal can be used.

[Other Embodiments] In the above embodiments, the case where the present invention is applied to the reproduction data of the optical disk has been described, but the reproduction data from the magnetic recording medium is also described.
The present invention can be applied in exactly the same manner.

[0072]

As described above, according to the present invention, the reproduction data extracting device is provided with the level comparison circuit for binarizing the reproduction data composed of the code capable of self-clocking by slicing it at a predetermined reference level. In, the phase of the PLL is synchronized with one of the rising edge and the falling edge of the pulse signal output from the level comparison circuit, and the phase difference between the output signal of this PLL and the other rising edge or the falling edge of the pulse signal is detected. Since the error signal corresponding to this phase difference is added to the reference level of the level comparison circuit, even if the reproduced data includes a DC component, the asymmetry state at the time of recording the original data can be determined with a relatively simple configuration. Can be compensated to expand the playback data detection window margin and reduce the playback data error rate Door can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a reproduction data extracting device according to the present invention.

FIG. 2 is a conceptual diagram showing a recording format of an embodiment of the present invention.

FIG. 3 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 5 is a conceptual diagram for explaining the operation of the embodiment of the present invention.

FIG. 6 is a conceptual diagram for explaining the present invention.

FIG. 7 is a block diagram showing a configuration example of a conventional reproduction data extracting circuit.

FIG. 8 is a block diagram showing the configuration of another conventional example.

[Explanation of symbols]

 30 Extraction Circuit 31 Comparator (Level Comparison Circuit) 32, 33 Envelope Detection Circuit 41 D-Type Flip-Flop Circuit 42 Rise Detection Circuit 43 Fall Detection Circuit 44 PLL 45 Phase Comparison Circuit 51 Resync Detection Circuit 52 Run Length Judgment Circuit

Claims (3)

[Claims] 1. A level comparison circuit for binarizing reproduced data composed of a code including a DC component and capable of self-clocking by slicing at a predetermined slice level, and a rising or falling edge of an output signal of the level comparison circuit. A phase synchronization circuit that generates a clock signal for the reproduction data that is phase-locked to one side, and a phase difference between the clock signal from this phase synchronization circuit and the other rising or falling edge of the output signal of the level comparison circuit. A reproduction data extracting device comprising a circuit for generating a corresponding error signal and an adder circuit for adding the error signal corresponding to the phase difference to the comparison slice level in the level comparing circuit. 2. The reproduction data extracting device according to claim 1, wherein the run length of a predetermined pattern in the reproduction data is judged and the judgment result is added to the error signal. 3. The reproduction data extracting device according to claim 1, wherein the time constant of the path of the error signal is different from the time constant of the path of the determination result.