JP2543092B2 - Digital data reproducing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting reproduction from a digital recording medium or detecting reception of digital transmission.

2. Description of the Related Art In a conventional digital data reproducing device, a normal PLL (phase locked loop) is used for an input value for clock reproduction. The PR (1,0, -1) type detection system and the clock recovery system will be described below as conventional examples. FIG. 4 is a block diagram of this conventional digital data reproducing apparatus, in which 1 is an equalizer for equalizing a received waveform to the PR (1,0, -1) system, and 2 is a digital value discrimination. A discriminator, 3 is a level shift for phase comparison, 4 is a phase comparator, 5 is a low pass filter (LPF), and 6 is a voltage controlled oscillator (VCO).

FIG. 5 shows an eye pattern of the output of the equalizer 1 in the conventional digital data reproducing apparatus configured as described above. In FIG. 5, the eye is open at two places, upper and lower, and the discrimination level has three values. Level shifter 3 in FIG.
Now, let's focus on the threshold level in Fig. 5. Then, the phase comparator 4 compares the oscillation waveform of the VCO 6 with the output of the level shifter 3, and the phase difference signal becomes LP.
It forms a PLL that controls VCO6 through F5. This VCO
The output of 6 is the regenerated clock, and the discriminator 2 uses this to restore the received signal to a digital value.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above configuration, as can be seen from FIG. 5, the timing at which the input waveform intersects the threshold level is shifted in the time axis direction due to the preceding and following digital values. I understand. This fluctuation in the time axis direction acts as noise when the phases are compared.
It will limit the performance of L. That is, the PLL becomes vulnerable to noise and has a problem that the gain cannot be sufficiently increased. Further, this configuration is premised on analog processing, and there is a problem that a similar clock recovery system cannot be constructed by digital processing using sample values.

In view of the above point, the present invention has an object to provide a digital data reproducing apparatus which is not affected by time axis fluctuation when obtaining a phase difference and is suitable for both analog processing and digital processing.

DISCLOSURE OF THE INVENTION The present invention relates to a discriminator for detecting a digital signal at a determination timing in a digital data reproducing apparatus which applies a binary signal to a transmission line and restores an original binary signal by a partial response method. And a pattern extractor for extracting only a specific pattern from the output value sequence of the discriminator, and a phase difference detection for capturing the specific pattern at a timing midway between the intervals of the determination timing and obtaining a clock phase difference from the captured value. And a transmitter for controlling the oscillation frequency of the clock according to the phase difference signal obtained from the phase difference detector, and the discrimination timing is created with the clock. Is.

Action The present invention has the above-described configuration, and a specific changing pattern in the discriminator output (for example, in ternary discrimination, -1
→ 1 and 1 → -1). Then, when the specific pattern is generated, the input value at the intermediate timing of the determination timing is read and the phase difference of the reproduced clock is detected, whereby the phase difference information with a small time axis fluctuation can be obtained. A PLL that controls the VCO is formed by this phase difference information. This method is also effective in analog processing, but even in digital processing in which the discriminator input is a sample value, the same configuration can be achieved by digital processing if the sample rate is set to twice the clock rate. Becomes In this case, it does not matter whether the discriminator performs binary discrimination or multi-value discrimination.

Embodiment 1 FIG. 1 shows a block diagram of a digital data reproducing apparatus in a first embodiment of the present invention. Also in the present embodiment, the PR (1,0, -1) method, which is the three-value discrimination, will be taken as an example.

In FIG. 1, 10 is an equalizer for waveform equalization in the PR (1,0, -1) system, 11 is a discriminator for performing 3-value discrimination, 12 is a latch, 13
Is a delay device that delays by half the data rate period, 14 is a pattern extractor that extracts a specific pattern from the discrimination output, 15 is a phase difference detector, and 16 is a low-pass filter (LP
F) and 17 are voltage controlled oscillators (VCO).

The operation of the digital data reproducing apparatus of this embodiment constructed as above will be described below. The eye pattern of the output of the equalizer 10 has a shape as shown in FIG. 2 similarly to the conventional example, and the discrimination level has three values (-1, 0, 1). Discriminator 1
The output of 1 passes through the latch 12, and the pattern extractor 14 extracts only a specific pattern based on the values before and after the latch 12. If there are only two types of this specific pattern, -1 → 1 and 1 → -1, the equalized output waveform between them takes the path as shown in FIG. If the equalized output is held at a timing just in the middle of the discrimination timing, the value represents the phase difference information of the clock. -1 → 1 and 1 →-
For 1 and 1, the sign of the hold value may be reversed. The function of the phase difference detector 15 is to perform pulse amplitude modulation with this value as a phase difference and output it. The phase difference signal is smoothed by LPF16 and becomes the control voltage of VCO17. And VCO17
The output of becomes the regenerated clock.

As described above, according to the present embodiment, when the specific pattern is extracted by the pattern extractor, the phase difference detector that reads the equalized output value and detects the phase difference at the intermediate timing of the determination timing is provided. As a result, it is possible to reproduce a clock with less fluctuation in the time axis and resistant to noise, and at the same time, reproduce and detect digital data.

FIG. 3 is a block diagram of a digital data reproducing apparatus showing a second embodiment of the present invention. In the figure, 20 is A / D
Converter, 21 is digital equalizer, 22 is discriminator, 23 is latch, 24 is 1/2 divider, 25 is latch, 26 is pattern extractor, 27 is phase difference detector, 28 is D / A Is a converter, 29 is a low pass filter (LPF), 30 is a voltage controlled oscillator (VCO), and 31 is an inverter whose clock phase is inverted.

The operation of the digital data reproducing apparatus of the second embodiment constructed as described above will be described below. Second
In this embodiment, the operation of the first embodiment is realized by digital processing. In FIG. 3, the oscillation frequency of the VCO 30 is twice the data rate frequency, and the A / D converter 20 and the equalizer 21 operate with a clock twice the data rate frequency. The input analog value is digitized by the A / D converter 20 and becomes the input of the equalizer 21. The equalizer 21 is a transversal filter for digital processing.

The discriminator 22 samples every other output of the equalizer 21 and discriminates and outputs it. Since the clock of the latch 25 has a phase opposite to that of the discriminator 22, data different from the data sampled by the discriminator 22 is sampled every other data. latch
The operations of 23 and the pattern extractor 26 are exactly the same as in the first embodiment, and only a specific pattern is extracted from the discriminator output. When the value of the latch 25 is read when this specific pattern is detected, the phase difference of the clock can be known. The phase difference detector 27 obtains this phase difference by digital processing, the D / A converter 28 converts it into an analog signal, the LPF 29 smooths it, and controls the VOC 30. The VCO 30 has the reference frequency set to twice the data rate as described above. VC in divider 24
By dividing the output of O30 by half, the clock regenerated at the same frequency as the data rate is obtained.

As described above, according to the present embodiment, the VCO oscillation frequency is set to the data rate of 2 even when digital processing is performed.
By doubling it, the clock can be reproduced without any trouble, and the discrimination output can be obtained at the same time. Similar to the first embodiment, the reproduced clock has a small time-axis fluctuation and is resistant to noise.

In addition, in the embodiment, PR (1,
Although the 0, -1) method has been described as an example, the discrimination level is 2
In the case of the value and the case of other multi-valued levels, the configuration can be exactly the same. Although two types of specific patterns, -1 → 1 and 1 → -1, were taken, the method of taking this pattern can be freely determined according to the case.

EFFECTS OF THE INVENTION As described above, according to the present invention, when reproducing digital data, it is possible to obtain a clock that is resistant to noise and has little time-axis fluctuation, and a large gain of the clock reproduction system can be obtained. Furthermore, the digital data suitable for not only analog processing but also digital processing can be reproduced, and its practical effect is great.

[Brief description of drawings]

1 is a block diagram of a digital data reproducing apparatus according to the first embodiment of the present invention, FIG. 2 is an operation waveform diagram of the same embodiment, and FIG. 3 is a digital data reproducing apparatus according to the second embodiment of the present invention. FIG. 4 is a block diagram of a conventional digital data reproducing apparatus, and FIG. 5 is an operation waveform diagram of the conventional example. 1 ... Equalizer, 2 ... Discriminator, 3 ... Level shifter, 4
...... Phase comparator, 5 …… Low pass filter, 6 …… Voltage controlled oscillator, 10 …… Equalizer, 11 …… Discriminator, 12 …… Latch, 13 …… Delayer, 14 …… Pattern extractor, 15 …… Phase difference detector, 16 …… Low pass filter, 17 …… Voltage controlled oscillator, 20 …… A / D converter, 21 …… Digital equalizer, 22
…… Discriminator, 23 …… Latch, 24 …… 1/2 divider, 25 ……
Latch, 26 ... Pattern extractor, 27 ... Phase difference detector,
28 …… D / A converter, 29 …… Low pass filter, 30 …… Voltage controlled oscillator, 31 …… Inverter.

Claims (1)

(57) [Claims] 1. A discriminator for detecting a digital signal at a discrimination timing, and a discriminator of the discriminator in a digital data reproducing apparatus which applies a binary signal to a transmission line and restores the original binary signal by a partial response method. A pattern extractor for extracting only a specific pattern from an example of output values, a phase difference detector for capturing the specific pattern at an intermediate timing of the discrimination timing interval, and obtaining a phase difference of clocks from the captured value, A digital data reproducing apparatus comprising an oscillator for controlling an oscillation frequency of the clock according to a phase difference signal obtained from a phase difference detector, and generating the discrimination timing with the clock.