JPH0660553A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To obtain a clock signal by which a reproducing signal is always sampled in optimum timing by detecting phase deviation in sampling based on an A/D converted signal and controlling the phase of a clock by a variable phase shift circuit. CONSTITUTION:A phase synchronizing generation circuit 2 consists of a phase detection circuit 3, a loop filter 4 and a voltage control oscillator 5. The clock signal CO whose rising agrees with timing in which the polarity of the reproducing signal R is changed, for example, is obtained. The clock signal CO is inputted in the variable phase circuit 6, phase-controlled based on a phase signal P, and then transmitted to an A/D converter 7 as a sampling clock C1. The reproducing signal R is sampled at the rising of the clock C1 in the converter 7, and the sampled result D is transmitted to an output terminal 9, then the phase in sampling is transmitted to a phase error detection circuit 8 and phase- adjusted. The circuit 8 outputs a phase control signal P based on the amplitude of signals before and after the code changing position of the output signal D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproduction signal for reproducing a clock signal from a reproduction signal of an optical disk or the like.

[0002]

2. Description of the Related Art When a recording signal on a recording medium such as an optical disk or a magnetic disk is digitally equalized, it is necessary to reproduce a read clock before judging the signal. FIG. 7 shows a circuit configuration when a clock signal is directly reproduced from a reproduced signal of a disc which is an analog signal. The phase-locked oscillator circuit 2 is composed of a phase detection circuit 3, a loop filter 4, and a voltage controlled oscillator 5. For example, the phase detection circuit 3
Serves to detect the difference between the rising timing of the clock C0 output from the voltage controlled oscillator 5 and the timing at which the polarity of the reproduction signal R input from the input terminal 1 changes, and bring it closer to zero. However, since the timing to be actually sampled by the A / D converter is the position where the eye of the reproduced signal opens, the clock C1 for sampling must be created by providing the phase shift circuit 22. Here, the amount of phase shift required for the phase shift circuit 22 depends on the frequency of the reproduced signal, the amount of delay of each part of the circuit, and the like, so that accurate adjustment is difficult.

The reproduced signal may include crosstalk from adjacent tracks. At this time, there is a method of removing the interference signal by using the reproduction signal from the target track and the reproduction signals from the adjacent two tracks which are the interference sources together and using an adaptive filter (Japanese Patent Application No. Hei 10 (1999) -135242). 3-40225). A conventional example in which this is realized by a digital circuit will be described with reference to FIG. Generally, the recording symbols of the respective tracks are not phase-synchronized, and in order to digitally process the reproduction signals R1 to R3 of the three systems, a clock signal based on the signal R1 from the reproduction target track is used. It is necessary to extract C0 and A / D convert the signals R2 and R3 of adjacent tracks. The reproduction signals of the three systems digitized at the rising edges of the clock signals C1 to C3 whose phases have been adjusted by the phase shift circuit are adaptive filters 19-1 to 19-19, respectively.
After the frequency characteristic is adjusted by -3, the adder 20
Is synthesized by. The output signal S from the adder 20 is sent to the output terminal 9 and the equalization error extraction circuit 21, and the error signal E is taken out.

When the output signal S includes the intersymbol interference component of the reproduction signal R1 and the crosstalk component from the adjacent track, the intersymbol interference component and the crosstalk component are extracted as the error signal E. The error signal E is input to each adaptive filter, and characteristic control is performed so that the error signal E approaches 0. When each adaptive filter has an ideal characteristic, only a component due to the influence of noise included in the reproduced signal appears in the error signal E. At this time, the signals DF2 and DF3 output from the adaptive filters 19-2 and 19-3 corresponding to the reproduced signals of the adjacent tracks correspond to those in which the polarities of the interference components included in the signal DF1 of the target track are inverted. There is. Here, when the timing of A / D converting the reproduced signal from the adjacent track is deviated from the timing of the crosstalk component included in DF1, the crosstalk removal characteristic is deteriorated, so that the phase shift circuit 22 is used. Timing adjustment of the sampling clock is important. However, as in the example of FIG. 7, accurate adjustment is difficult due to variations in the delay amount of each circuit portion and changes in the reproduced signal frequency.

[0005]

In the conventional clock recovery circuit, it is necessary to adjust the phase of the clock signal output from the phase-locked oscillator circuit by using a phase shift circuit so as to be suitable for sampling the recovery signal. It was Moreover, the required amount of phase shift depends on the frequency of the reproduced clock, variations in circuit elements, and environmental temperature changes, making it difficult to maintain the clock phase appropriately. When sampling is performed at a timing deviated from the optimum point, there is a problem that the noise margin of the reproduced signal is reduced and the error rate is increased.

The object of the present invention is to solve the above problems.
Unaffected by the frequency of the reproduction clock and variations in the elements,
It is an object of the present invention to provide a clock recovery circuit that can always sample a recovered signal with an optimum phase.

[0007]

According to the present invention, there is provided a clock reproducing circuit for reproducing a clock signal based on a data signal read from a recording medium such as an optical disk, the frequency of which corresponds to a clock component with the data signal as an input. A phase-locked oscillator circuit that outputs a signal, a variable phase-shift circuit that changes and outputs the phase of the output of the phase-locked oscillator circuit based on a phase control signal, and an output signal of the variable phase-shift circuit as a sampling clock. An A / D converter for sampling a data signal, and a phase error detection circuit for generating the phase control signal based on the digital amplitude data output from the A / D converter are provided.

[0008]

When the clock signal is reproduced from the reproduced signal by the phase locked oscillator, the frequency becomes equal to the clock required for ideal sampling, but the phase deviates from the optimum point. In the present invention, the phase shift of sampling is detected based on the A / D converted signal, and the phase of the clock is controlled by the variable phase shift circuit, so that the reproduced signal can be sampled at the optimum timing without difficult phase adjustment. A clock signal can be obtained.

[0009]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing an embodiment. The phase-locked oscillation circuit 2 is composed of a phase detection circuit 3, a loop filter 4, and a voltage controlled oscillator 5 as in the conventional example. As a result, for example, the clock signal C0 having a rising edge that matches the timing at which the polarity of the reproduction signal R changes can be obtained. This clock signal is input to the variable phase circuit 6 and phase-controlled on the basis of the phase control signal P, and then A as the sampling clock C1.
It is sent to the / D converter 7. In the A / D converter, the reproduction signal R
Is sent at the rising edge of the clock C1 and the result D is sent to the output terminal 9 and also sent to the phase error detection circuit 8 to adjust the sampling phase. The phase error detection circuit 8 outputs the phase control signal P based on the signal amplitude before and after the sign change position of the output signal D.

FIG. 2 is a block diagram showing the details of a configuration example of the phase error detection circuit 8. This circuit receives the output signal D from the A / D converter 7 as an input and outputs a phase control signal P. After the binary decision circuit 11 makes a binary decision on D, the delay circuit 10, the inverter 12, and the AND circuit 13 detect the sign inversion position. Input signal D to time T
When the signal before and after the delayed signal is the trailing edge of the signal, SC1 becomes active, and conversely when the leading edge of the signal falls, SC2 becomes active. Switch 14
-1, 14-2 are closed when SC1 and SC2 become active, respectively, and operate so that the input signal D or a signal whose sign is inverted is input to the integrator.

Next, the operation of the phase error detection circuit 8 with respect to the sampling phase shift will be described with reference to FIG. The input signal D is a reproduction signal R sampled at the rising edge of the clock C1. If the timing deviates from the ideal phase φ0 and becomes the phase of φ1, for example,
The control signal SC1 becomes active before and after the fall of the input signal. The integrator 16 has a point Q1 immediately before the fall.
A1 and the amplitude A2 of the point Q2 immediately after are added, so that the phase control signal P is equivalently added with an amplitude proportional to the amplitude AM of the midpoint QM linearly interpolated from the two points Q1 and Q2. It was done. Since the amplitude of this midpoint takes a negative value on average, the value of P decreases. Similarly, since SC2 becomes active before and after the rising signal, the same operation as that obtained by subtracting a value proportional to the amplitude of the midpoint of the two points from P is equivalently performed. In this case as well, the amplitude of the midpoint takes a positive value on average and acts in the direction of decreasing P. Since the variable phase shift circuit 6 works to delay the phase of the clock signal C1 as the phase control signal P decreases, the sampling phase approaches the optimum point φ0. When the phase reaches the optimum point φ0, the midpoints of the rising edge and the falling edge of the input signal both substantially coincide with 0, so that the phase control signal P is maintained at a constant value.

FIG. 4 is a block diagram showing another example of the phase error detection circuit 8. When the input signal D to the phase error detection circuit 8 is a ternary signal, the input signal is ternary judged by the two judging circuits 11-1 and 11-2. Here, the output of the decision circuit 11-1 becomes active when the input signal D exceeds the positive threshold value. Also, the determination circuit 11
The -2 output is active when D is above the negative threshold. The output of the decision circuit 11-2 becomes active when D exceeds the negative threshold value. Delay circuit 10,
The inverter 12 and the AND circuit 13 detect the sign change position of the input signal D as in the example of FIG. 2 and are sent to the switches 14-1 and 14-2 via the OR circuit 17 so that the input signal D It acts so that the signal whose sign is inverted is input to the integrator. The phase error detection circuit can be similarly realized when the input signal is a multi-valued signal having four or more values.

FIG. 5 shows an embodiment in which the output signal of the digital filter is input to the phase error detection circuit 8.
When the data recording density is high, it is difficult to directly judge the signal D output from the A / D exchanger 7 in binary or in multivalue. In such a case, by providing the digital filter 18, the signal DF equalized for easy determination can be used as the input of the phase error detection circuit.

FIG. 6 shows an example of a circuit configuration when the present invention is applied to a circuit for removing crosstalk between tracks by using an adaptive filter. The reproduction signal R1 from the target track is input from the input terminal 1-1, and the reproduction signals R2 and R3 from the two tracks adjacent to the target track are input from the input terminals 1-2 and 1-3. Since the output signal from the adaptive filter 19-1 becomes an equalized signal including a crosstalk component, the phase error detection circuit 8-1 works similarly to the example of FIG. Further, the output signals DF2 and DF3 from the adaptive filters 19-2 and 19-3 approach signals in which the sign of the crosstalk component included in DF1 is inverted. By inputting these to the phase error detection circuits 8-2 and 8-3,
The sampling phase for R2 and R3 can be kept optimal for crosstalk removal.

[0015]

By using the clock recovery circuit of the present invention, it is possible to obtain a clock signal suitable for digital processing without a sampling phase shift, regardless of the frequency change of the input signal and the variation of the circuit elements.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of the present invention.

FIG. 2 is a system diagram showing a configuration example of a phase error detection circuit.

FIG. 3 is a diagram for explaining the operation of a phase error detection circuit.

FIG. 4 is a system diagram showing a configuration example of a phase error detection circuit worthy of a multilevel signal.

FIG. 5 is a system diagram showing another embodiment of the present invention.

FIG. 6 is a system diagram showing still another embodiment of the present invention.

FIG. 7 is a system diagram showing a conventional clock recovery circuit.

FIG. 8 is a system diagram showing another conventional clock recovery circuit.

[Explanation of symbols]

 1 Input Terminal 2 Phase-locked Oscillation Circuit 6 Variable Phase Shifting Circuit 7 A / D Converter 8 Phase Error Detection Circuit 9 Output Terminal 11 Judgment Circuit 14 Switch 16 Integrator 18 Filter 19 Adaptive Filter 21 Equalization Error Extraction Circuit 22 Phase Shifting Circuit

Claims (1)

[Claims] 1. A clock recovery circuit for reproducing a clock signal based on a data signal read from a recording medium such as an optical disk, and a phase-locked oscillation circuit for outputting a signal having a frequency corresponding to a clock component with the data signal as an input. A variable phase shift circuit for changing and outputting the phase of the output of the phase locked oscillator circuit based on a phase control signal; and an A / D for sampling the data signal using the output signal of the variable phase shift circuit as a sampling clock. A clock recovery circuit comprising a converter and a phase error detection circuit for generating the phase control signal based on digital amplitude data output from the A / D converter.