JP3591295B2 - Playback clock extraction device - Google Patents

Description

【００１１】
その結果、積分等化で２値の場合は信号の極性が変わる部分ではデータの和（平均値）、信号の極性が変わらない部分ではデータの差として位相誤差信号が得られる。
【００１２】
また、微分等化で３値の場合は、記録信号の極性が変わる部分で正または負の微分パルスが発生するが、この部分では３値検出で１または−１の判別結果が得られ、結局、位相誤差信号は１または−１の判別結果が得られるタイミングの前後のデータから得られる。
【００１３】
ここで、信号列｛ａｎ｝に対する３値判別結果を（表２）のようにおくと、位相誤差信号は、同じく（表２）のようになる。
【００１４】
【表２】

【００１５】
ここで、０以外が続くとき、ａ７とａ８は完全にキャンセルされ、ａ６，ａ９も位相情報を持たない。
【００１６】
再生されたディジタルデータの積分等化した信号より再生クロックを抽出する再生クロック抽出装置としては、特開平８−１０６７２８号公報「磁気再生復号装置」が知られている。
【００１７】
図５に、この従来の再生クロック抽出装置の構成を示す。
図５において、再生信号を積分等化器２１で積分等化し、Ａ／Ｄ変換器２２で再生信号のデータレートの２倍のクロックで量子化し、復号器２３でＡ／Ｄ変換器２の出力のうち奇数サンプルデータから再生データを復号し、位相誤差演算回路２４でＡ／Ｄ変換器２２の出力から偶数サンプルデータに対して前後の奇数サンプルデータの極性が反転したときだけ、前の奇数サンプルデータの極性と掛け算して位相誤差を演算し、Ｄ／Ａ変換器２５でアナログ信号に変換された位相誤差に基づいて電圧制御発振器（ＶＣＯ）２６を制御し、Ａ／Ｄ変換器２２のサンプリングクロックを制御する。１／２分周器２７は電圧制御発振器（ＶＣＯ）２５出力のサンプリングクロックを１／２分周して再生クロックを出力する。ここで、Ａ／Ｄ変換器２２の出力が奇数サンプルデータを出力するとき再生クロックの極性は正（＋１）としている。
【００１８】
位相誤差演算回路２４はＤ−フリップフロップ２４１の出力にＤ−フリップフロップ２４２の出力の極性（ＭＳＢ）を乗算する乗算器２４３と、Ｄ−フリップフロップ２４１の入力とＤ−フリップフロップ２４２の出力の極性（ＭＳＢ）の符号が異なるとき出力１を出力する排他的論理和２４４と、１／２分周器２７出力が１で排他的論理和２４４の出力が１のとき、ＡＮＤ回路２４５により乗算器２４３出力を位相誤差信号として出力するゲート回路２４６から成る。
【００１９】
ここで、信号列｛ｂｎ｝に対する２値判別結果（ＭＳＢ）を（表３）のようにおくと、位相誤差信号は、同じく（表３）のようになる。
【００２０】
【表３】

【００２１】
【発明が解決しようとする課題】
しかしながら上記のような従来の図４の再生クロック抽出装置では、積分等化ではオフセットがないが、同期情報を持たない変化のない点からノイズが混入する、微分等化では、波形の変化が続く点の部分から位相情報が取り出せない、それぞれの出力に瞬時的に大きなオフセットを発生する、という問題点を有していた。ここで、オフセットとは瞬時位相誤差信号における信号成分の残留成分を意味し、最終的にはＰＬＬループの積分効果でキャンセルされるが、クロックの瞬時位相に影響を与えるものである。
【００２２】
また、図４の再生クロック抽出装置では、Ａ／Ｄ変換器の前のアナログによる波形等化が必須で、波形等化が行われていない、あるいは、等化残りがあるような状態では、生成される再生クロックに位相ずれが発生すること、波形等化をデジタルで行うとき、波形等化がＰＬＬループ内にはいるため、波形等化とＰＬＬの収束を同時に行わなければならず、情報量の不足で、収束が遅い、誤収束するという問題点を有していた。
【００２３】
さらに、３値判別するときの量子化器１３において判別余裕を持たせるために、正値スレッシュレベルを小さめに、負値スレッシュレベルを大きめに設定しておく必要があるが、その結果として、本来の位相収束点の他に、クロックの位相が半周期ずれた点に誤った位相収束点が存在することになってしまうという問題点を有していた。
【００２４】
また、図５は積分等化に適した方式で、微分波形には極性が不明な中間値があるため、これをこのまま微分等化に応用することが出来ない、さらに、検出した位相誤差に大きなオフセットが生じ、瞬時的な位相ずれ（位相ジッタ）が発生するという問題点があった。
【００２５】
本発明は、上記従来の問題点を解決するもので、再生信号の変化点が有するすべての位相情報が利用できるとともに瞬時的なオフセットがない位相誤差信号が作成でき、かつ、本来のクロック位相収束点の他に誤った位相収束点が発生することがない再生クロック抽出装置を提供することを目的とする。
【００２６】
【課題を解決するための手段】
この課題を解決するために本発明は、Ａ／Ｄ変換のサンプリングをデータレートの２倍のレートのサンプリングクロックで行い、誤差演算手段は、３値判別手段の出力が変化する再生データの間のＰＬＬデータを用いて位相誤差を演算するものであって、再生データの微分波が孤立波の場合、その両側のＰＬＬデータの差を取りオフセットをキャンセルし、再生データの変化がデータレートごとに連続する場合、その最前端と最後端で発生するオフセットを直接加算または減算してキャンセルする。
【００２７】
これにより、再生信号の変化点が有するすべての位相情報を利用出来ると共に、瞬時的なオフセットがない位相誤差信号が作成でき、瞬時位相ジッタの少ない再生クロックを生成できる。
【００２８】
かつ、波形等化が行われていない、あるいは、等化残りがあるような状態でタイミング誤差演算を行っても、位相ジッタの少ない再生クロックを生成でき、等化回路をＰＬＬループ内に設けた場合でもＰＬＬループは等化回路の収束状態に大きく影響されずに収束し、等化回路はＰＬＬループが収束するに伴い最適値へ収束し、最終的に両者共、最適値へ収束する。
【００２９】
【発明の実施の形態】
本発明の第１の発明は、記録媒体から再生された信号をデータレートの２倍のレートのサンプリングクロックで量子化する量子化手段と、前記量子化手段が出力するサンプルデータを微分波形に等化し、１サンプリングクロックおきに再生データとＰＬＬデータを交互に出力する等化手段と、前記等化手段が出力する再生データを基準値に対し正値（＋）か零値（０）か負値（−）かの３値判別を行う３値判別手段と、前記３値判別手段の判別結果が変化する連続する２つの再生データの間のＰＬＬデータを用い、前記３値判別手段の判別結果の変化の極性、データ配列に基づいて位相誤差を演算する位相誤差演算手段と、前記量子化手段に供給するサンプリングクロックを生成するサンプリングクロック生成手段と、前記位相誤差演算手段の位相誤差出力に基づいて、サンプリングクロックの位相と発信周波数を制御するサンプリングクロック制御手段と、前記サンプリングクロックを２分周して前記再生データの再生クロックを生成する再生クロック生成手段とを備えたものであり、前記位相誤差演算手段は、前記３値判別手段の判別結果において、零値（０）の間に存在する単独の零値以外（±）および連続する零値以外（±）のグループに対し、前記グループ前端における零値（０）から零値以外（±）に変化する再生データの間のＰＬＬデータと前記グループ終端における零値以外（±）から零値（０）に変化する再生データの間のＰＬＬデータを加減算して、これらのＰＬＬデータが有するオフセットをキャンセルして出力するので、瞬時位相ジッタを少なくできるという作用を有し、零値以外（±）と零値以外（±）の間のオフセットのないＰＬＬデータを、２つの連続する再生データの変化の方向に応じて極性変換して出力するので、再生信号が有するすべてに位相情報を有効に利用でき、応答性と収束性に優れたＰＬＬループを構成出来るという作用を有する。
【００３０】
また、本発明の第２の発明は、３値判別結果が正値が連続または負値が連続するとき正値または負値の最も確からしい１つを残し他はすべて零値の検出出力を出力することにより、誤ったＰＬＬデータの選択の確率を減少し、誤った位相に疑似ロックするのを防止するという作用を有する。
【００３１】
以下、本発明の実施の形態について、図面を用いて説明する。
（実施の形態１）
図１は、この実施の形態１の再生クロック抽出装置の構成例を示すブロック図である。
【００３２】
図１において、量子化手段としてのＡ／Ｄ変換回路３２は、記録媒体から再生された信号をデータレートの２倍のレートのサンプリングクロックでサンプリングしてデジタルデータとして出力する。等化回路３１はＡ／Ｄ変換回路３２が出力するデジタルデータを微分波形に等化し、１サンプリングクロックおきに再生データとＰＬＬデータを交互に出力する。ここで、等化回路３１は従来例と異なりＡ／Ｄ変換器３２の後に配置する。
【００３３】
３値判別回路３３は、等化回路３１が出力する再生データを基準値に対し正値（＋）か零値（０）か負値（−）かの３値判別を行う。位相誤差演算回路３４は、３値判別手段出力のデータ配列を検出し、３値判別手段の検出結果が正値（＋）または負値（−）である再生データの前後のＰＬＬデータとパターン検出手段で検出されたデータ配列に基づいて位相誤差を演算する。サンプリングクロック位相制御回路３５は誤差演算手段が出力する誤差演算結果に基づいて、サンプリングクロック生成回路（ＶＣＯ）３６が生成するサンプリングクロックの位相と発振周波数を制御する。ＶＣＯ３６からのサンプリングクロックは、Ａ／Ｄ変換回路３２に入力されると共に、１／２分周器３７で２分周することにより上記再生データに同期した再生クロックを生成する。
【００３４】
微分等化波形は、一つの変化点に対し一つの微分パルスを発生するため、正値（＋）または負値（−）は２連続することがないが、ＰＬＬのロック位相が１８０度ずれると微分パルスのピーク値の両側をサンプリングすることになり、正値または負値が連続することがあり、本来の検出点とは異なったデータを選択することになり、誤ったロック点に収束するか収束が遅れることになる。
【００３５】
本発明の第２の発明は、３値判別手段３３として３値判別結果が正値（＋）または負値（−）が連続するとき正値（＋）または負値（−）の最も確からしい１つを残して他はすべて零値（０）に変更して出力するもので、最も確からしい選択手段として、たとえば、最も絶対値が大きいものを選択する方法がある。
【００３６】
位相誤差演算回路３４は零値（０）と零値以外（±）の間、零値以外（±）と零値（０）の間のＰＬＬデータを直接加減算してそれぞれのＰＬＬデータが有するオフセットをキャンセルして出力する。
【００３７】
図２は、位相誤差演算回路３４の具体的な構成を示すブロック図である。
図２において、パターン変換回路３４１は３値判別出力の変化の方向、特定パターンを検出し切換器（ＳＷ）３４３、３４６の制御信号、記憶手段であるＤフリップフロップ３４４のデータ読み込み指令信号を出力する。乗算器３４２はＰＬＬデータに−１を乗じて符号変換し、切換器（ＳＷ）３４３は２つの連続する３値判別出力の変化の方向に応じてＰＬＬデータまたは符号変換したＰＬＬデータを出力する。記憶手段であるＤフリップフロップ３４４は再生データの変化が零値（０）から零値以外（±）に変化するとき、切換器（ＳＷ）３４３の出力を読み込む。加算器３４５は切換器（ＳＷ）３４３の出力とＤフリップフロップ３４４記憶値を加算平均する。切換器（ＳＷ）３４６は零値（０）から零値（０）に変化するときおよび零値（０）から零値以外（±）に変化するとき０を出力し、零値以外（±）から零値以外（±）に変化するとき切換器（ＳＷ）３４３の出力を位相誤差出力として出力し、零値以外（±）から零値（０）に変化するとき加算器３４５の出力を位相誤差出力とする。
【００３８】
加算平均は入力の和の１／２であるが、理想的には１／√２倍であって、収束点では零になるのでそれほど精度は要求されないため、単なる和でも良いし、適当な乗数を掛けたものでも良い。
【００３９】
ここで、信号列｛ｂｎ｝に対する３値判別結果を（表４）のようにおくと、位相誤差信号は、同じく（表４）のようになる。
【００４０】
【表４】

【００４１】
図３は本実施の形態の動作を説明する図であって、上記信号列｛ｂｎ｝に対応している。
【００４２】
図３（１）は等化回路３１により等化された波形図、図３（２）は切換器３４３の出力すなわち従来例図５に相当する出力であり、図３（３）は本発明の位相誤差出力であって、符号変換器出力に存在したオフセットは本発明の位相誤差出力ではすべて、キャンセルされている。なお、塗りつぶした部分は位相誤差信号成分を示す。
【００４３】
以上のように、本実施の形態によれば、再生信号の微分等化した信号の変化点が有するすべての位相情報を利用出来ると共に、微分波形特有の符号間干渉を受けた波形でも記録パターンの違いにより発生する位相誤差への信号成分の漏れ込みをキャンセルし、瞬時的なオフセットがない位相誤差信号が作成でき、瞬時位相ジッタの少ない再生クロックを生成でき、また、再生信号を微分波形に等化し復号する系において、収束前の波形等化が行われていない、あるいは、等化残りがあるような状態でタイミング誤差演算を行っても、位相ジッタの少ない再生クロックを生成できるので、等化回路３１をＰＬＬループ内に設けた場合でもＰＬＬループは等化回路３１の収束状態に大きく影響されずに収束し、等化回路３１はＰＬＬループが収束するに伴い最適値へ収束し、最終的に両者共、最適値へ収束する再生クロック抽出装置が得られる。
【００４４】
【発明の効果】
以上のように、本発明によれば、次の効果を奏する。
【００４５】
（１）再生信号の微分等化した信号の変化点が有するすべての位相情報を利用出来ると共に、微分波形特有の符号間干渉を受けた波形でも記録パターンの違いにより発生する位相誤差への信号成分の漏れ込みをキャンセルし、瞬時的なオフセットがない位相誤差信号が作成でき、瞬時位相ジッタの少ない再生クロックを生成できる。
【００４６】
（２）再生信号を微分波形に等化し復号する系において、収束前の波形等化が行われていない、あるいは、等化残りがあるような状態でタイミング誤差演算を行っても、位相ジッタの少ない再生クロックを生成できるので、等化回路をＰＬＬループ内に設けた場合でもＰＬＬループは等化回路の収束状態に大きく影響されずに収束し、等化回路はＰＬＬループが収束するに伴い最適値へ収束し、最終的に両者共、最適値へ収束する。
【図面の簡単な説明】
【図１】本発明の実施形態１による再生クロック抽出装置の構成を示すブロック図
【図２】同再生クロック抽出装置を構成する位相誤差検出器の具体構成を示すブロック図
【図３】同再生クロック抽出装置を構成する位相誤差検出器の動作を示す波形図
【図４】従来の再生クロック抽出装置の構成を示すブロック図
【図５】従来の積分等化用再生クロック抽出装置の構成を示すブロック図
【符号の説明】
３１ 等化回路
３２ Ａ／Ｄ変換器
３３ ３値判別回路
３４ 位相誤差演算回路
３５ クロック位相制御回路
３６ 電圧制御発振器
３７ １／２分周器
３４１ パターン検出器
３４２ 乗算器
３４３、３４６ 切換器
３４４ Ｄ−フリップフロップ
３４５ 加算器[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention generates a clock for an A / D converter or a digital processing circuit that is phase-synchronized with a reproduction signal when the reproduction signal from a recording medium such as a magnetic tape or a magnetic / optical disk is subjected to analog / digital conversion and digital processing. The present invention relates to a synchronous clock generation device suitable for performing the above.
[0002]
[Prior art]
In the case of a recording / reproducing apparatus capable of recording and reproducing digital data such as digital audio signals and digital video signals on a recording medium, a reproduction signal is used to detect digital data from a signal reproduced from the recording medium during reproduction. Is supplied to a PLL circuit (phase locked loop circuit), and the PLL circuit extracts a clock included in the reproduced signal, and detects digital data in synchronization with the extracted clock.
[0003]
Conventionally, such a reproduced signal has synchronization information, that is, clock phase information, in a changed portion of the signal.
[0004]
Further, as a reproduced clock extracting device capable of extracting a reproduced clock from both signals of a differentiated signal and an integrated waveform of a reproduced signal, see IEICE Transactions, C-II, Vol. J75-C-II, No. 11, the type described in the invited paper "Recent developments in signal processing technology for magnetic disks" on pages 611 to 623 is known.
[0005]
FIG. 4 shows the configuration of this conventional recovered clock extraction device.
In FIG. 4, a reproduction signal reproduced from a recording medium and waveform-equalized by an equalization circuit 11 is sampled and quantized by an A / D conversion circuit 12 at a sampling clock having the same rate as the data rate of the reproduction signal. It is output as reproduction data. The quantizer 13 discriminates the input digital data into binary, ternary, etc., and when discriminating ternary data, discriminates it as "1" if it is larger than a positive threshold level, and if it is smaller than a negative threshold level. In this case, it is determined to be "-1", and if it is between them, it is determined to be "0" and the result of the determination is output.
[0006]
The phase error calculation circuit 14 extracts phase error data between the digital reproduction data and the sampling clock. The phase error data is converted into an analog signal by the D / A converter 15, and the control signal of the voltage controlled oscillator (VCO) 16 Is done.
[0007]
A loop including the A / D converter 12, the phase error calculation circuit 14, the D / A converter 15, and the VCO 16 forms a PLL loop.
[0008]
The output of the quantizer 13 is 1 or -1 for binary discrimination corresponding to integral equalization, and 1, 0, -1 for ternary discrimination corresponding to differential equalization. The phase error detection circuit 14 includes D flip-flops 141 and 142, multipliers 143 and 144, and a subtractor 145, and multiplies the current digital data by the output of the quantizer 13 one clock before to obtain 1 The digital data before the clock is multiplied by the current output of the quantizer 13, and the result is subtracted and output as a phase error calculation result.
[0009]
Here, if the result of the binary determination for the signal sequence {an} is as shown in (Table 1), the phase error signal is also as shown in (Table 1).
[0010]
[Table 1]

[0011]
As a result, in the case of binary by integration equalization, a phase error signal is obtained as a data sum (average value) in a portion where the signal polarity changes, and a data difference in a portion where the signal polarity does not change.
[0012]
Also, in the case of ternary differential equalization, a positive or negative differential pulse is generated in a portion where the polarity of the recording signal changes. In this portion, a ternary detection results in 1 or −1, and eventually a discrimination result is obtained. , The phase error signal is obtained from data before and after the timing at which the determination result of 1 or -1 is obtained.
[0013]
Here, if the ternary discrimination result for the signal sequence {an} is set as shown in (Table 2), the phase error signal also becomes as shown in (Table 2).
[0014]
[Table 2]

[0015]
Here, when a value other than 0 continues, a7 and a8 are completely canceled, and neither a6 nor a9 has phase information.
[0016]
As a reproduction clock extraction device for extracting a reproduction clock from a signal obtained by integrating and equalizing the reproduced digital data, Japanese Patent Application Laid-Open No. 8-106728 “Magnetic reproduction decoding device” is known.
[0017]
FIG. 5 shows the configuration of this conventional recovered clock extraction device.
In FIG. 5, the reproduction signal is integrated and equalized by an integration equalizer 21, quantized by an A / D converter 22 with a clock twice the data rate of the reproduction signal, and output from the A / D converter 2 by a decoder 23. Out of the odd-numbered sample data, the phase-difference calculating circuit 24 outputs the previous odd-numbered sample only when the polarity of the odd-numbered sampled data before and after the even-numbered sampled data from the output of the A / D converter 22 is inverted. A phase error is calculated by multiplying by the polarity of the data, and a voltage controlled oscillator (VCO) 26 is controlled based on the phase error converted into an analog signal by the D / A converter 25, and sampling of the A / D converter 22 is performed. Control the clock. The 分 frequency divider 27 divides the frequency of the sampling clock output from the voltage controlled oscillator (VCO) 25 by １ ／ and outputs a reproduced clock. Here, when the output of the A / D converter 22 outputs odd-numbered sample data, the polarity of the reproduced clock is positive (+1).
[0018]
The phase error calculation circuit 24 multiplies the output of the D-flip-flop 241 by the polarity (MSB) of the output of the D-flip-flop 242, and the input of the D-flip-flop 241 and the output of the D-flip-flop 242. When the sign of the polarity (MSB) is different, an exclusive OR 244 that outputs an output 1 is output. When the output of the 分 divider 27 is 1 and the output of the exclusive OR 244 is 1, a multiplier is output by the AND circuit 245. 243 output as a phase error signal.
[0019]
Here, when the binary decision result (MSB) for the signal sequence {bn} is set as shown in (Table 3), the phase error signal is also as shown in (Table 3).
[0020]
[Table 3]

[0021]
[Problems to be solved by the invention]
However, in the conventional reproduction clock extracting apparatus of FIG. 4 as described above, although there is no offset in the integral equalization, noise is mixed in because there is no change without synchronization information. In the differential equalization, the waveform changes continuously. There is a problem that phase information cannot be extracted from a point portion and a large offset is instantaneously generated in each output. Here, the offset means a residual component of the signal component in the instantaneous phase error signal, which is eventually canceled by the integration effect of the PLL loop, but affects the instantaneous phase of the clock.
[0022]
Further, in the reproduced clock extraction device of FIG. 4, it is necessary to perform waveform equalization using an analog signal before the A / D converter. When the reproduced clock is phase-shifted and the waveform equalization is performed digitally, the waveform equalization is in the PLL loop. Therefore, the waveform equalization and the convergence of the PLL must be performed at the same time. However, there is a problem that convergence is slow and erroneous convergence is caused due to lack of data.
[0023]
Further, in order to allow the quantizer 13 to perform the ternary discrimination, it is necessary to set the positive threshold level to be small and the negative threshold level to be large in order to provide a margin for discrimination. In addition to the phase convergence point, there is a problem that an incorrect phase convergence point exists at a point where the phase of the clock is shifted by a half cycle.
[0024]
FIG. 5 shows a method suitable for integral equalization. Since the differential waveform has an intermediate value whose polarity is unknown, it cannot be applied to differential equalization as it is, and the detected phase error is large. There is a problem that an offset occurs and an instantaneous phase shift (phase jitter) occurs.
[0025]
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, in which all phase information of a change point of a reproduction signal can be used, a phase error signal having no instantaneous offset can be created, and the original clock phase convergence can be achieved. It is an object of the present invention to provide a reproduced clock extracting apparatus in which an erroneous phase convergence point does not occur in addition to points.
[0026]
[Means for Solving the Problems]
In order to solve this problem, according to the present invention, the A / D conversion is sampled by a sampling clock having a rate twice as high as the data rate, and the error calculating means performs the processing between the reproduced data in which the output of the ternary discriminating means changes. A phase error is calculated using the PLL data. When the differential wave of the reproduction data is an isolated wave, the offset is canceled by taking the difference between the PLL data on both sides thereof, and the change of the reproduction data is continuously changed for each data rate. In this case, the offset generated at the forefront end and the rearmost end is directly added or subtracted to cancel.
[0027]
As a result, all the phase information of the change point of the reproduction signal can be used, a phase error signal having no instantaneous offset can be created, and a reproduction clock with little instantaneous phase jitter can be generated.
[0028]
In addition, even if the timing error calculation is performed in a state where the waveform equalization is not performed or the equalization remains, a reproduced clock with little phase jitter can be generated, and the equalization circuit is provided in the PLL loop. Even in this case, the PLL loop converges without being greatly affected by the convergence state of the equalizer circuit, and the equalizer circuit converges to the optimum value as the PLL loop converges, and finally both converge to the optimum value.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
According to a first aspect of the present invention, there is provided a quantizing means for quantizing a signal reproduced from a recording medium with a sampling clock having a rate twice as high as a data rate, and converting sample data output by the quantizing means into a differential waveform. Equalizing means for alternately outputting reproduced data and PLL data every other sampling clock; and reproducing data output by the equalizing means with a positive (+), zero (0), or negative value with respect to a reference value. (-) and ternary judging means for performing Kano ternary determination, using the PLL data between two reproduction data continuous determination result of the ternary determination means changes, the discrimination result of the ternary determination means Phase error calculating means for calculating a phase error based on the polarity of change and data array, sampling clock generating means for generating a sampling clock to be supplied to the quantizing means, and phase error calculating means Based on the phase error output, which includes a sampling clock control means for controlling the phase and the oscillation frequency of the sampling clock, and a reproduction clock generation means for said sampling clock divided by two to generate a reproduction clock of the reproduction data , and the said phase error calculating means, the determination result of the ternary discriminating means, a group of non-zero values of the single present (±) and non-continuous zero values to (±) between the zero value (0) On the other hand, the PLL data between the reproduction data that changes from zero value (0) to a non-zero value (±) at the front end of the group and the reproduction data that changes from non-zero value (±) to zero value (0) at the end of the group Is added and subtracted, and the offset of these PLL data is canceled and output, so that instantaneous phase jitter can be reduced. It has a function, the PLL data without offset between the non-zero values (±) other than zero value (±), since the polarity conversion outputs depending on the direction of change in two successive reproduced data, reproduction The phase information can be effectively used for all of the signals, and a PLL loop having excellent responsiveness and convergence can be formed.
[0030]
Further, according to the second invention of the present invention, when the ternary determination result is a continuous positive value or a continuous negative value, a detection output of a zero value is output except for the most likely positive or negative value. By doing so, there is an effect that the probability of selecting erroneous PLL data is reduced, and false locking to an erroneous phase is prevented.
[0031]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of the reproduction clock extraction device according to the first embodiment.
[0032]
In FIG. 1, an A / D conversion circuit 32 as a quantization means samples a signal reproduced from a recording medium with a sampling clock having a rate twice as high as a data rate, and outputs it as digital data. The equalization circuit 31 equalizes the digital data output from the A / D conversion circuit 32 into a differential waveform, and alternately outputs reproduced data and PLL data every other sampling clock. Here, the equalizing circuit 31 is arranged after the A / D converter 32, unlike the conventional example.
[0033]
The ternary discrimination circuit 33 performs a ternary discrimination of the reproduced data output from the equalization circuit 31 with respect to a reference value as a positive value (+), a zero value (0), or a negative value (-). The phase error calculation circuit 34 detects the data array of the output of the ternary discriminating means, detects the PLL data before and after the reproduced data whose detection result of the ternary discriminating means is a positive value (+) or a negative value (-), and detects a pattern. The phase error is calculated based on the data array detected by the means. The sampling clock phase control circuit 35 controls the phase and the oscillation frequency of the sampling clock generated by the sampling clock generation circuit (VCO) 36 based on the error calculation result output from the error calculation means. The sampling clock from the VCO 36 is input to the A / D conversion circuit 32 and is also divided by two by a 分 frequency divider 37 to generate a reproduction clock synchronized with the reproduction data.
[0034]
In the differential equalized waveform, one positive pulse (+) or negative value (-) does not continue two times because one differential pulse is generated for one change point, but when the lock phase of the PLL is shifted by 180 degrees. Since sampling is performed on both sides of the peak value of the differentiated pulse, positive or negative values may be continuous, data different from the original detection point will be selected, and it will converge to the wrong lock point. Convergence will be delayed.
[0035]
According to the second invention of the present invention, when the ternary determination result is a positive value (+) or a negative value (-) successively, the ternary determination means 33 is most likely to be a positive value (+) or a negative value (-). All but one are changed to zero value (0) and output. One of the most probable selection means is, for example, a method of selecting the one having the largest absolute value.
[0036]
The phase error calculation circuit 34 directly adds / subtracts PLL data between the zero value (0) and the non-zero value (±) and between the non-zero value (±) and the zero value (0), and offsets each PLL data. Is canceled and output.
[0037]
FIG. 2 is a block diagram showing a specific configuration of the phase error calculation circuit 34.
In FIG. 2, a pattern conversion circuit 341 detects the direction of change of the ternary discrimination output, a specific pattern, and outputs a control signal for switches (SW) 343 and 346 and a data read command signal for a D flip-flop 344 serving as storage means. I do. The multiplier 342 multiplies the PLL data by −1 to perform code conversion, and the switch (SW) 343 outputs PLL data or code-converted PLL data according to the direction of change of two successive ternary discrimination outputs. The D flip-flop 344 serving as a storage means reads the output of the switch (SW) 343 when the change of the reproduction data changes from zero value (0) to a value other than zero value (±). The adder 345 adds and averages the output of the switch (SW) 343 and the value stored in the D flip-flop 344. The switch (SW) 346 outputs 0 when changing from zero value (0) to zero value (0) and when changing from zero value (0) to other than zero value (±), and outputs other than zero value (±). The output of the switch (SW) 343 is output as a phase error output when the output changes from zero to a value other than zero (±), and the output of the adder 345 is output when the output changes from a value other than zero (±) to zero (0). Error output.
[0038]
The averaging is one half of the sum of the inputs, but ideally it is 1 / 倍 2 times, and since it becomes zero at the convergence point, so little accuracy is required. May be multiplied by.
[0039]
Here, when the ternary discrimination result for the signal sequence {bn} is set as shown in (Table 4), the phase error signal also becomes as shown in (Table 4).
[0040]
[Table 4]

[0041]
FIG. 3 is a diagram for explaining the operation of the present embodiment, and corresponds to the signal sequence {bn}.
[0042]
FIG. 3A shows a waveform diagram equalized by the equalizing circuit 31, FIG. 3B shows an output of the switch 343, that is, an output corresponding to FIG. 5 of the related art, and FIG. Any offset present in the phase error output, which is present in the output of the transcoder, is canceled in the phase error output of the present invention. The shaded portion indicates the phase error signal component.
[0043]
As described above, according to the present embodiment, all phase information of a change point of a signal obtained by differentiating and equalizing a reproduced signal can be used, and a waveform subjected to intersymbol interference peculiar to a differentiated waveform can be used to record a recorded pattern. Cancels the leakage of signal components into the phase error caused by the difference, creates a phase error signal without instantaneous offset, generates a playback clock with little instantaneous phase jitter, and converts the playback signal into a differentiated waveform. In a decoding and decoding system, even if waveform equalization before convergence is not performed or a timing error calculation is performed in a state where there is a residual equalization, a reproduced clock with little phase jitter can be generated. Even when the circuit 31 is provided in the PLL loop, the PLL loop converges without being greatly affected by the convergence state of the equalization circuit 31, and the equalization circuit 31 converges on the PLL loop. Converges to the accompanying optimum value that eventually Both, clock recovery apparatus is obtained which converge to an optimum value.
[0044]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
[0045]
(1) It is possible to use all phase information of a change point of a signal obtained by differentiating and equalizing a reproduced signal, and to generate a signal component for a phase error generated due to a difference in a recording pattern even in a waveform subjected to intersymbol interference peculiar to a differentiated waveform. , A phase error signal having no instantaneous offset can be created, and a reproduced clock with little instantaneous phase jitter can be generated.
[0046]
(2) In a system for equalizing and decoding a reproduced signal into a differentiated waveform, even if the waveform equalization before convergence is not performed or the timing error calculation is performed in a state where the equalization remains, even if the phase error is calculated, Since a small number of reproduced clocks can be generated, even when an equalizer is provided in the PLL loop, the PLL loop converges without being greatly affected by the convergence state of the equalizer, and the equalizer is optimized as the PLL loop converges. Converge to a value, and finally both converge to an optimal value.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a reproduced clock extracting device according to a first embodiment of the present invention; FIG. 2 is a block diagram showing a specific configuration of a phase error detector included in the reproduced clock extracting device; FIG. FIG. 4 is a waveform diagram showing the operation of a phase error detector constituting the clock extraction device. FIG. 4 is a block diagram showing the configuration of a conventional reproduction clock extraction device. FIG. 5 shows the configuration of a conventional reproduction clock extraction device for integration and equalization. Block diagram [Explanation of symbols]
31 equalization circuit 32 A / D converter 33 ternary value discrimination circuit 34 phase error calculation circuit 35 clock phase control circuit 36 voltage controlled oscillator 37 1/2 frequency divider 341 pattern detector 342 multipliers 343, 346 switcher 344 D -Flip-flop 345 adder

Claims (3)

Quantizing means for quantizing a signal reproduced from a recording medium with a sampling clock having a rate twice as high as a data rate;
Equalizing means for differentiating and equalizing the sample data output by the quantization means and alternately outputting reproduced data and PLL data every other sampling clock;
Ternary discriminating means for performing a ternary discriminating of the reproduced data output by the equalizing means with respect to a reference value as a positive value (+), a zero value (0), or a negative value (-);
A phase error for calculating a phase error based on a polarity and a data array of a change in the determination result of the ternary determination unit using PLL data between two consecutive reproduction data in which the determination result of the ternary determination unit changes. Arithmetic means;
Sampling clock generation means for generating a sampling clock to be supplied to the quantization means,
Sampling clock control means for controlling the phase and transmission frequency of the sampling clock based on the phase error output of the phase error calculation means,
Reproduction clock generation means for generating a reproduction clock of the reproduction data by dividing the sampling clock by 2;
The phase error calculating means determines, with respect to the group of non-zero values (±) and continuous non-zero values (±) existing between zero values (0) in the determination result of the ternary determining means , Between the PLL data at the front end of the group between the reproduced data that changes from zero value (0) to non-zero value (±) and the reproduced data at the end of the group that changes from non-zero value (±) to zero value (0). A reproduction clock extracting apparatus for adding and subtracting PLL data to cancel and output an offset of the PLL data. The ternary discriminating means, when the ternary discrimination result is a series of positive values (+) or a series of negative values (-), changes all other values to zero (0) except for the most likely one, and outputs the result. The reproduced clock extracting device according to claim 1. The phase error calculation means has a polarity switching means for switching the polarity of the PLL data, a storage means, and an addition means,
The polarity switching means switches the polarity of the PLL data according to the direction of change of two consecutive ternary determination results,
Change in the ternary determination result, when the zero value (0) other than zero value of (±), writes the output of said polarity switching means to said memory means, other than zero value from non-zero values (±) of (±) when the output of the polarity switching unit and phase error output, when the non-zero value (±) zero value (0), and averaging the stored value in the adding means output and said memory means of said polarity switching means 3. The reproduced clock extracting device according to claim 1, wherein the reproduced clock extracting device outputs a phase error output.

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