JPH0129109B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly practical digital signal receiving circuit that has a small received data error rate and does not cause signal quality deterioration.

One of the optimal reception methods for digital signals with added noise is an integral judgment method. Especially when the noise is white Gaussian noise, optimal reception with a small error rate is performed. FIG. 1 shows an example of the configuration of a digital signal receiving circuit to which this method is applied, which receives an NRZ signal with added noise.
The received input digital signal is supplied to an integrator 1, and is also guided to a clock (CK) extractor 2 to extract a clock signal having a period T from the above signal. This clock signal is delayed by a minute time (Δτ) via the delay circuit 3 and applied to the integrator 1. As a result, the integrator 1 has its integral value reset for the first minute period of one cycle, and then integrates the received input digital signal. This integration operation is repeated every cycle. The integrated value output from the integrator 1 is supplied to a comparator 4 and successively compared with a preset comparison reference voltage 5. The voltage value of this comparison reference voltage 5 is set to a/2 _(v) , for example, if the level of the NRZ signal takes a value from 0 _(v) to a _(v) . Then, the comparator 4 outputs, for example, a "1" level signal when the integrated value output exceeds the comparison reference voltage value, and a "0" level signal otherwise, which is sent to the flip-flop 6. is applied to the data input terminal. This flip-flop 6 latches at the trailing edge of the clock signal extracted by the clock extractor 2, and therefore the judgment output of the comparator 4 is 1 of the input digital signal.
It will be latched at the end of the cycle and the data will be output.

Therefore, according to the receiving circuit configured in this manner, the noise components included in the received input digital signal for one period are averaged by the integration processing of the received input digital signal by the integrator 1, and thereby Data judgment becomes possible without being affected by noise.

Now, when realizing such a receiving circuit with a digital circuit, the receiving input digital signal with waveform distortion that is led to the integrator 1 is processed with a period T/N (however, N>
If the above signal is sampled in step 1), the level of the value is determined to obtain a "0" or "1" level signal, and this signal is cumulatively added over a 1-bit period T to obtain a digital integral value. good. and,
If the integral value is larger than a predetermined value N/2, this may be determined as data "1".

However, if the receiving circuit is simply converted into a digital circuit in this way, for example, the S/N of the received signal
When the clock signal is lowered, jitter occurs in the clock signal extracted by the clock extractor 2, and as a result, there is a disadvantage that the data error rate increases. Furthermore, when the received signal is a PSK signal, the signal obtained by multiplying and detecting the received modulated signal and the regenerated carrier wave is similar to the NRZ signal described above, but the multiplicative detection output signal in which the modulated signal is band-limited is The waveform becomes a sine wave. Therefore, the amplitude of the modulated signal becomes small near the data conversion point, and it is greatly affected by noise.
Therefore, a large amount of jitter occurs in the baseband signal that is the detection output, resulting in a problem that the data error rate becomes extremely large.

The present invention has been made in consideration of these circumstances, and its purpose is to provide a highly practical digital signal receiving circuit that has a low data error rate and can perform signal processing digitally and easily. It's about doing.

The outline of the present invention is to divide a received input digital signal into a plurality of time slots, determine the signal level, and accumulate a signal train over one bit time slot period, that is, one data period of the input digital signal. When performing addition and digital integration, weighting processing is performed using weighting coefficients that are set in advance in stages so that the weight at the center of one data cycle becomes heavier in accordance with the time slot for the signal sequence. In this way, the data error rate is improved and the above-mentioned objective is effectively achieved.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a circuit configuration diagram for explaining the basic concept of the present invention, and is composed of a time division circuit A, a multiplication/integration circuit B, a comparison/judgment circuit C, and a timing generation circuit D. Further, each of these circuits A, B, C, and D is entirely digitally constructed.

Now, the received input digital signal is guided to the time division circuit A and also to the timing generation circuit D. This timing generation circuit D is
A clock reproducing circuit 10 reproduces and extracts the clock signal contained in the input digital signal, and outputs a clock signal CK having a period T corresponding to one bit period of the input digital signal. A multiplier circuit 11 inputting this clock signal CK multiplies the clock signal CK by N to produce a high-speed clock signal with a period of T/N.
HCK is generated and supplied to the time division circuit A and the multiplication/integration circuit B, respectively. on the other hand,
The clock signal CK is input to a delay circuit 12 and delayed by a time _τ1 . Further, the delayed output from this delay circuit 12 is inputted to a second delay circuit 13, where it is further delayed by a time τ ₂ . Delayed output of clock signal CK by these delay circuits 12 and 13
CK ₍ 〓 ₁₎ and CK ₍ 〓 ₂₎ are used as counter reset signals and count prohibition signals, which will be described later, in the multiplication/integration circuit B.
are given respectively. In response to the timing-controlled signal output from the timing generating circuit D, data reproduction of the received input digital signal is performed.

Now, the time division circuit A is realized by a determination circuit 14 constituted by, for example, a limiting amplifier, and a flip-flop (FF) 15 which performs a latch operation in response to the high speed clock signal HCK.
The determination circuit 14 discriminates the received input digital signal at a predetermined level due to waveform distortion due to noise.
The waveform is shaped into a signal consisting of a "1" or "0" level, and the flip-flop 15 divides this signal into a plurality of time slots in accordance with the high speed clock signal HCK. As a result, the output signal of the time division circuit A becomes time division data whose level has been determined with a period of T/N.

The time-division data of the received input digital signal whose data format has been converted through the time-division circuit A is taken into the counter 17 through the gate circuit 16 of the multiplication and integration circuit B. This gate circuit 16 performs a gate operation in response to the high speed clock signal HCK, whereby the time-divided data is extracted for each time slot. The counter 17 sequentially counts the data extracted through the gate circuit 16, and its counting operation is performed using the delayed clock signal.
Controlled by CK ₍ 〓 ₁₎ and CK ₍ 〓 ₂₎ . That is, the clock signal CK ₍ 〓 ₁₎ is applied to the counter 17 as a reset signal, and the counter 17 sets its count value to "0" when time τ ₁ has passed from the start of one data period.
has been reset to . In other words, the data input at this time τ ₁ is multiplied by a weighting coefficient "0" and counted, and does not actually contribute to the count of the counter 17. Further, the clock signal CK ₍ < ₂₎ applied to the counter 17 after a time τ ₂ has elapsed from this reset timing is used for inhibit control, that is, to stop the counting operation of the counter 17. Therefore, data input during this time τ ₂ is multiplied by a weighting coefficient of “1” and subjected to counting, and data input after this time τ ₂ is multiplied by a weighting coefficient of “0” again. is multiplied and controlled so that it does not contribute to counting. In other words, the data is counted only during the time τ ₂ , and the counter 17 cumulatively counts the data "1" during this period. Furthermore, the assignment of weighting coefficients is indicated by whether or not counting by the counter 17 is enabled, and the weighting of "0" or "1" is applied to the data according to the divided time slots. It turns out.

Therefore, the counter 17 counts the weighted data over one data period, and calculates the data "1".
A count value corresponding to the number of objects will be obtained. In particular, in the above-mentioned example of weighting "0" or "1", weighting that emphasizes data in a stable central data area excluding the leading and trailing edges of one data period is applied. It corresponds to doing. The count value of the data weighted in this way is then led to the comparator 18 of the comparison/judgment circuit C, and compared with the comparison reference value. This comparison reference value is set to, for example, M/2 since the number of time slots mentioned above is N and the number of time slots used for counting is M (N>M). Then, in the comparator 18, the count value by the counter 17 is N/
When it exceeds 2, it is determined that the bit data is "1" and "1" data is output; otherwise, "0" data is output. This judgment data is latched in flip-flop 19 and then output.

Figure 3 a to i are signal waveform diagrams showing the operation of the circuit shown in Figure 2 above, and figure a is a signal waveform diagram showing the operation of the circuit shown in Figure 2 above.
The figure shows a received input digital signal consisting of an NRZ signal, and the signal is sent to the time division circuit A as shown in Figure b.
The level is determined as shown in . 3c shows a clock signal CK reproduced from the received input digital signal, d shows a high-speed clock signal HCK obtained by multiplying the clock signal CK, and e,
f indicates the signal waveforms of the delayed clock signals CK ₍ 〓 ₁₎ and CK ₍ 〓 ₂₎ , respectively. However, counter 17
extracts the signal shown in FIG. 3b at time slots divided by the high speed clock signal HCK shown in FIG. 3d and counts the extracted signal to obtain the counted value shown in FIG. 3g. In this example, since M=5, the comparator 18 compares the above counted values using 5/2 as the comparison reference value, and when the counted value exceeds 5/2, a judgment is made as shown in Fig. 3h. I am getting output. This judgment output is latched in the flip-flop 19 at a timing delayed by one data period, and is outputted as shown in FIG. 3i.

As described above, according to the present circuit, data divided into a plurality of time slots is weighted with "1" or "0", and this is counted by the counter 17. In this embodiment, the control of whether or not to allow the counter 17 to count data corresponds to the above-mentioned weighting of "1" or "0". This weighting invalidates the data that is affected by noise near the data conversion point, digitally integrates the judgment results in the center of the data, and discriminates the data based on the integration results. It is possible to significantly reduce data judgment errors caused by jitter in the baseband signal caused by the small amplitude of the modulated signal. In other words, it is possible to significantly improve the data error rate. Moreover, great effects can be expected by simple signal processing called the weighting process described above.

Figure 4 shows the results of an experiment on the bit error rate when the ratio between the data counting period and the data period (one bit period) in the counter 17 was changed, with the horizontal axis showing the above ratio and the vertical axis showing the bit error rate. Error rates are shown. As is clear from the results of this experiment, when the ratio R is set to about 0.7, that is, when the weighting coefficient near the data conversion point is set to "0", it is possible to significantly improve the bit error rate.
Note that setting R=0 means instantaneous judgment of data, and it is clear that the bit error rate improvement effect of this circuit is very large even when compared with this instantaneous judgment. Therefore, it is confirmed that the weighting process in this circuit is simple and has a very large effect on improving the bit error rate.

Now, FIG. 5 is a block diagram showing a main part of an embodiment of the present invention, and shows an example of a characteristic structure of the multiplication/integration circuit B. In FIG. What is shown here inputs data divided into a plurality of time slots to a multiplier 20,
After being multiplied by weighting coefficients sequentially read out from the memory 21 corresponding to the time slots, the multiplication output is input to the adder 22 for cumulative addition. This adder 22 receives the clock signal
It is reset at the rising point of CK, and the comparison/determination circuit C for determining the output of this adder 22 is configured to determine and detect the added value data immediately before the reset. Further, the memory 21 sequentially reads out preset weighting coefficients in synchronization with the high speed clock signal HCK.

Thus, if a received input digital signal whose triangular wave polarity changes depending on the data is input to a signal receiving circuit equipped with such a multiplication/integration circuit B, for example, as shown in FIG. The level is determined in the time division circuit A as shown in FIG. 6b. Further, the timing generating circuit D generates a clock signal CK shown in FIG. 6c from the above digital signal.
d in the same figure according to this clock signal CK.
It generates the high-speed clock signal HCK shown in the figure below.
In response to this high-speed clock signal, the memory 21 sets the weighting coefficients to, for example, "1" and "2" as shown in FIG. 6e.
The input signals are read out as "3", "4", "5", "4", etc., and the input signals are weighted by the multiplier 20. Therefore, the cumulative addition value of the weighted data by the adder 22 changes as shown in FIG. For example, it is possible to obtain output data as shown in FIG. In other words, the S/N of the input digital signal is
Since the amplitude of the triangular wave varies depending on the amplitude at each time, effective data can be obtained by weighting according to the amplitude (here, a proportional example is shown) and then digitally integrating it to determine its level. Playback occurs. Even in this case, it is possible to significantly improve the bit error rate as in the previous embodiment.

Note that the weighting coefficients set in advance in the memory 21 may be determined in accordance with the waveform of the received input digital signal, and the signal to be received is not limited to the NRZ signal. Also here, the multiplier 20
has shown an example in which when the judgment output data becomes "1", the weighting coefficient value is outputted as data, and when the above data becomes "0", the polarity of the weighting coefficient value is inverted and the data is outputted, but this is not particularly limited. Needless to say.

Although the embodiments of the digital signal receiving circuit according to the present invention have been described above, the present invention is not limited only to these embodiments.

In the embodiment, the clock signal is extracted from the received input digital signal and multiplied to generate a high-speed clock signal. Specifically, as shown in FIG. 7, a tank circuit 31 is used to extract the clock signal from the input digital signal. Extract the resonance output and send this resonance output to the judge 3
The high speed clock signal may be obtained through the multiplier 33 after the waveform is shaped using the clock signal 2.

In addition, as shown in FIG.
5. Using the phase comparator 36 and low frequency filter 37
A PLL circuit is constructed, and the high-speed clock signal is extracted from the oscillator 34 after the loop is stabilized by comparing the phase with the clock component of the received input digital signal which is waveform-shaped and extracted through the determiner 38. Of course, it is fine to do so.

Furthermore, if the received signal is a PSK signal or FSK signal, the carrier wave signal can be used as it is as a high-speed clock signal. Therefore, in this case, the configuration of the timing generation circuit D can be greatly simplified, which has many practical advantages. In short, the present invention can be implemented with various changes without departing from the gist thereof, and the weighting coefficient settings and the like may be determined according to the specifications.

As described in detail above, according to the present invention, it is possible to significantly improve the data (bit) error rate with relative simplicity, and it has tremendous effects such as making it possible to implement an all-digital circuit extremely effectively. A highly practical digital signal receiving circuit that achieves this can be provided here.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an example of a conventional circuit, FIG. 2 is a circuit configuration diagram for explaining the basic concept of the present invention, and FIGS. 3 a to 3 are operational waveform diagrams of the circuit shown in FIG. Fig. 4 is a characteristic diagram of experimental data showing the effect of improving the bit error rate, Fig. 5 is a main part configuration diagram showing an embodiment of the present invention, and Figs. The operational waveform diagrams of FIGS. 7 and 8 are diagrams each showing an example of the configuration of a circuit for generating a high-speed clock signal. A... Time division circuit, B... Multiplication/integration circuit, C... Comparison/judgment circuit, D... Timing generation circuit, 10... Clock extraction circuit, 11... Multiplication circuit, 12, 13... Delay circuit, 14... Judgment circuit, 15, 19 ...flip-flop, 16...gate circuit, 17...counter,
18... Comparator, 20... Multiplier, 21... Memory, 2
2... Adder, 31... Tank circuit, 32... Determiner,
33... Multiplier circuit, 34... Oscillator, 35... Frequency divider,
36... Phase comparator, 37... Low frequency device, 38... Judgment device.

Claims (1)

[Claims] 1. A time division circuit that divides the 1-bit time slot period of the received input digital signal into a plurality of time slots and determines the signal level in each time slot, and a plurality of time slots formed by dividing the 1-bit time slot period. A memory storing weighting coefficients set in advance in stages over three or more values such that the weight at the center of the 1-bit time slot period increases correspondingly, and a multiplication circuit that applies a predetermined weight to the signal of each time slot by multiplying the signal whose level has been determined by the time division circuit by a weighting coefficient stored in the memory; The present invention includes an integrating circuit that integrates the received input digital signal over a 1-bit time slot period, and a comparison circuit that compares the integral value output obtained by the integrating circuit with a predetermined value to discriminate the signal. Features a digital signal receiving circuit.