JPS59178841A - Data receiving circuit of failure supervisory device - Google Patents

Abstract

PURPOSE:To improve the reliability of receiving data through a transmission line with low quality by combining and identifying the results of receiving signals sampled by a data collecting device in plural timings delayed from a synchronizing signal in a supervisory device of polling system. CONSTITUTION:Plural timing pulses having different phase from each other delayed from the synchronizing signal from a terminal Q1 are generated by an oscillator 1 and a ripple counter 2. The signals of adjacent bits in a waveform of a returned data signal from plural terminal devices 5 are overlapped as shown in Fig. (g). FFs 6, 7 and 8 fetch the input signal by the outputs of Qn-2, Qn-1 and Qn of the counter 2 respectively and the outputs are as shown in figs. h-j. Since the point of time of fetch is delayed by >=1/2 period of the synchronizing signal, the preceding receiving signal is vanished and an accurate data is fetched. A comparator 9 outputs a high level when the summing value of the input signal is larger than a prescribed value as shown in Fig. (k). The weighted mean is attained by using resistors R1, R2 and R3 different in resistance value. An FF10 outputs a receiving data at the succeeding synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data receiving circuit for a polling type monitoring device.

Recently, computers have been introduced into equipment for monitoring abnormalities such as fires and gas leaks, and a polling method has been used to collect abnormality information from a plurality of terminal devices.

In the above-described system, a high-quality transmission path is required to accurately receive return data from each terminal. However, in fire alarm devices and the like, a data collection device and a plurality of terminal devices are generally connected by a balanced line. Balanced lines cause distortion in transmission waveforms due to capacitance and the like, and are susceptible to noise interference, making it difficult to obtain sufficient reliability.

In view of the above-mentioned circumstances, an object of the present invention is to provide a data receiving circuit for an abnormality monitoring device that can improve the reliability of data received through a low-quality transmission line.

The receiving circuit of the present invention calls a plurality of terminal devices connected to a transmission line from the data collection device side using an address signal,
Fire information from the called terminal.

In a polling-type abnormality monitoring device that returns abnormality information such as gas leak information, the data collection device sends a synchronization signal and an address signal to the transmission path, and the data collection device sends a synchronization signal and an address signal to the transmission path, and the data collection device transmits a synchronization signal and an address signal with a delay of 1/2 or more of a synchronization signal cycle from the synchronization signal. timing pulse generating means for generating a plurality of timing pulses of mutually different phases; a plurality of flip-flops for respectively setting return data from the terminal device with timing pulses output from the timing pulse generating means; It is characterized by comprising an adder that adds the outputs of the flip-flops, and identifying returned data based on the output of the adder.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. That is, the clock oscillator 1 generates a clock pulse train of a constant period. The ripple counter 2 sends out a synchronizing signal from the output terminal Q1 to the line L1 in response to the first pulse of the clock pulse train. Ripple counter 2 output Q
2 to ζ are at high level for one clock period by the second to nth pulses, respectively, and are 0. However, Q in the second half, r Qn
-1r Q? ? , -2 only. No. yv+
With one pulse, the output Q becomes high level, and the ripple counter 2 operates cyclically. FIG. 2(a) shows the output pulse train of the clock oscillator 1, and FIG. 2(b) shows the waveform of the output Q1 of the ripple counter 2, that is, the synchronization signal.
Figures (C) and (d).

(e) is the output Q7L-2 of ripple counter 2, respectively.
+Qn-s r The waveform of Qn is shown. That is, a synchronization signal is output every n clocks, and the output is Q%-2+Q?
L-1+Q? From L, timing pulses are output which are delayed by 1/2 or more of the synchronizing signal cycle from the synchronizing signal, and whose phases differ from each other by one clock. In this embodiment, the oscillator 1 and the ripple counter 2 constitute a timing pulse generating means that generates a plurality of timing pulses of mutually different phases delayed from the synchronization signal.

A start signal, an address signal, and a stop signal to be sent to the line are input in parallel to the shift register 3.
It is set by the output Q□ of counter 4. The counter 4 outputs 71Qrr when it counts m synchronization signals.
Set L to No-I level. The signal set in the shift register 3 is serially transmitted one bit at a time using the synchronizing signal as a clock, and is sent out to the line L2, and the next address signal is set by the (m+1)th synchronizing signal and is sent out again as a serial signal. The value of m is greater than or equal to the total number of bits of the start signal, address signal, stop signal, and return data. Therefore, as shown in FIG. 2(f), an address signal is output to the line L2 following the start signal, and a stop signal (not shown) is further output to the line L2.

Each of the plurality of terminal devices 5 uses the synchronization signal on the line L1 as a clock signal and monitors the address signal on the line L2, and when receiving the address signal specifying itself, transmits fire information etc. as a digital data signal to the line L3. Send upward. Of course, the data signal is serially transmitted one pit at a time in synchronization with the synchronization signal. The return data signal is on line L.
3 is transmitted and input to the data collection device side. As shown in Figure 2 (gl), the waveform of the input signal is a waveform in which the rising edge is slow and the falling edge is trailing, and the signals of adjacent pits overlap with each other.Such a received data signal is input to the data output of a plurality of 7 flip-flops 6°7.8.Flip-flop 6 receives the input signal through the Q7-2 output of ripple counter 2, and flip-flop 7 receives the input signal through the Q%-4 output. The flip-flop 8 receives an input signal through a basket output.

Therefore, the flip-flops 6 to 8 are arranged as shown in FIGS. 2(h), (i), and (j), respectively. Since the data acquisition time of each flip 70 is delayed by more than 1/2 of the synchronization signal period, the previous received signal has sufficiently disappeared, and the current received signal has risen sufficiently, so accurate data can be obtained. can be imported.

Then, the outputs of the flip-flops 6 to 8 are input to the comparator 9 through resistors R, , R2, and R3, respectively, and the comparator 9 outputs a constant value by adding the above input signals as shown in FIG. 2(k). A high level appears when the value is higher than the value. For example, when the values of the resistors R1, R2 and R3 are equal, the input signal is identified by a majority vote of the outputs of the flip 70 knobs 6-8.

Further, for example, by making the resistance values of the resistors R1, R2, and R3 different, it is possible to treat the edge of the flip-flop 8 as the most weighted signal.

In this case, more accurate data identification is possible by adding weight closer to the end of the synchronization signals.

The output signal of the comparator 9 is set in the 7-lip-flop 10 by the next synchronizing signal as shown in FIG. 2 (4), and is output as received data.

In this embodiment, the received signal is transferred to a plurality of flip-flops 6 to 6.
Since the timing to set the bit to 8 is given by the timing pulse output in the latter half of the synchronization signal period output by the ripple counter 2, the data can be read when the received signal rises sufficiently and the received signal 1 bit before has sufficiently disappeared. This has the effect that it is less susceptible to distortion of the received waveform due to input, line capacitance, etc. Further, by capturing the received signal in a plurality of 7-lips and 70-tubes at different timings, it is possible to reduce the influence of noise. In other words, it reduces the effects of distortion and noise on the received waveform,
This has the effect of being able to obtain received data with high reliability even if a low quality transmission path is used.

Figure 3 shows a synchronization signal generated by a pair of transmission lines.

FIG. 7 is a signal waveform diagram showing another embodiment of the present invention in which an address signal and a return signal are exchanged.

In this case, data "1" is represented by signal A having a low level period of 1/4 interval at the rear end of 1-teta interval T as shown in FIG. Data "0" is represented by signal B that divides one data interval T into four and outputs high, low, high, low as shown in the figure (C). Following the start bit of signal A, the address signal consisting of a combination of signals A and H, and the stop bit of signal B, a synchronization signal is sent out.

The synchronization signal is a waveform in which signal B is continuously transmitted.

During the low level period of the synchronization signal, the output side of the sending circuit (not shown) is grounded, and the output side of the sending circuit (not shown) is grounded.
A current flows in due to the returned data signal as shown in cl). If this inflow current is detected by, for example, a photodiode inserted in series with the line, and the light emitted from the photodiode is photoelectrically converted, an electrical signal corresponding to the returned data current can be obtained.

By inputting this electrical signal as a received data signal to the plurality of flip-flops 6 to 8 shown in FIG. 1, correct data can be restored from the received signal with waveform distortion using the same timing as in the above embodiment. It is possible.

To identify the received signal as described above, for example, one bit of the returned data is read from the input port multiple times at different timings in synchronization with the synchronization signal and delayed, and "1" and 2 are determined based on the calculation results of the multiple read data. It can also be implemented by software to determine ``0''.

As described above, in the present invention, a synchronization signal is sent from the data collection device side, return data is sent out from the terminal side in synchronization with the synchronization signal, and the received signal is sent to a plurality of channels delayed from the synchronization signal. Since it is configured to identify received data by combining the results of sampling at different timings,
Accurate data restoration is possible by reducing the effects of waveform distortion and noise due to transmission line capacitance, etc. Therefore, there is an effect that highly reliable received data can be obtained even if a low quality transmission path is used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart showing various signals of the above embodiment, and FIG. 3 is a time chart showing another embodiment of the invention. In the figure, 1...clock oscillator, 2...ripple counter, 3...shift register, 4 counter, 5...
・Terminal device, 6-8, 10...Flip-flop, 9・
...Comparator (710 calculator). Applicant Nittan Co., Ltd.

Claims (1)

[Claims] (1) Polling in which a plurality of terminal devices connected to a transmission line are called by an address signal from the data collection device side, and abnormal information such as fire information and gas leak information is returned from the called terminal devices. In the above abnormality monitoring device, the data collection device sends a synchronization signal and an address signal to the transmission path, and generates a plurality of timing pulses of mutually different phases that are delayed by 1/2 or more of a synchronization signal period from the synchronization signal. a plurality of flip-flops each setting return data from the terminal device according to a timing pulse output from the timing pulse generation means; and an adder for adding the outputs of the plurality of flip-flops. A data receiving circuit for an abnormality monitoring device, comprising: identifying returned data based on the output of the adder. (2. In the data receiving circuit of the abnormality monitoring device according to claim 1, the adder weights and adds the outputs of a plurality of flip-flops. (3) Claim In the data receiving circuit of the abnormality monitoring device according to item 1, the data collecting device sends out the address signal and the synchronization signal in series, and the current returned from the terminal device in synchronization with the synchronization signal. The device is characterized in that it comprises a current detection means for detecting a signal, and the output of the current detection means is inputted to the plurality of seven lip-flops.