JP2776325B2 - Duty measurement circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duty measuring circuit, and more particularly to a digital circuit terminating circuit in a RZ circuit.
The present invention relates to a duty measurement circuit for monitoring a clock extraction unit of a received signal encoded by a (Return to Zero) code.

[0002]

2. Description of the Related Art A conventional duty measuring circuit of this kind is constructed as follows.
Either an analog circuit is included, or a digital system is used in which a counter circuit measures the time between the rising and falling points of the received extracted clock using a higher frequency clock signal. I was

[0003]

In a conventional duty measuring circuit, when an analog circuit such as a low-pass filter is used, the duty measurement of a high-frequency signal has a problem in terms of transient responsiveness. There is a problem that adjustment is required due to variations in the characteristics of the parts.

Further, in the case of the digital system, an oscillator having a higher frequency than the reception extraction clock, a counter circuit operable at a high operation frequency, and the like are required. Was.

Accordingly, the present invention has solved the above problems,
Provided is a duty measurement circuit that is suitably applicable to monitoring of a clock extraction unit of a reception signal encoded by an RZ code of a digital line termination circuit and that can measure a duty without requiring a high-frequency oscillator. The purpose is to:

[0006]

SUMMARY OF THE INVENTION A duty measuring circuit according to the present invention comprises a 1-bit length of a received signal in a duty measuring circuit of a receiving section of a signal coded by an RZ code on a line in a digital line terminating device. The cycle of minutes is T
Multiphase clock generation for generating and sending out n polyphase clocks each delayed by kT / n (where n is the resolution, k = 1, 2,..., N) with respect to the reference clock Circuit and the multi-phase clock generated by the multi-phase clock generation circuit , and the n multi-phase clocks
Detecting a logic level of the received RZ signal at the time in defined, sometimes normal detection signal matches the value logical level predetermined plurality of outputs sometimes abnormality detection signal mismatch (n pieces) And the output results of the plurality of detection circuits for the n multi-phase clocks are received, and among the n detection results, m normal detection signals are detected on the time axis.
(However, m ≦ n) If detected continuously , this m and the previous
And a duty determination circuit that determines and encodes the duty of the received signal from n .

According to the present invention, the period of the signal under measurement is represented by T.
And a predetermined phase (= kT) with respect to the reference clock.
/ N, where k = 1, 2,... N), a clock generating means for generating and outputting a plurality of (n) clocks shifted by k, and a time point determined by each of the plurality of clocks
At a value that matches a predetermined value for the signal under measurement .
Detecting means for detecting whether or not the reference clock is signal delay means for detecting the duty of the signal under measurement based on the detection result of the detecting means for the plurality of clocks. By detecting the presence or absence of a pulse of the signal under measurement at each clock edge of the multi-phase clock delayed by a predetermined phase, it is possible to obtain the pulse duration in one pulse cycle based on the detection result, An oscillator for generating a higher frequency clock, which has been a problem when digitally measuring the duty of the pulse signal, and for counting the period (pulse duration) between the rise and fall of the pulse signal using the clock. The duty can be measured without using a counter or the like.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a timing waveform chart for explaining an embodiment of the present invention, and AMI (Al
(ternation Mark Inversion) shows a determination result based on a received signal and a multiphase clock.

Referring to FIG. 1, multi-phase clock generation circuit 1
Then, the reference clock generated by the oscillator 5 is input, and n
Δφ = kT / n (where T is one bit length of the received signal, n
Generates n polyphase clocks delayed by the resolution k = 1, 2,..., N).

First to n-th pattern detection circuits 2-1 to 2-n
Input the multi-phase clocks generated by the multi-phase clock generation circuit 1 and input the multi-phase clocks to the edges of the input clocks .
It takes to detect a pattern in the received signal (logic level).

First to n-th pattern detection circuits 2-1 to 2-n
Outputs a normal detection signal when a pattern is detected, and outputs an abnormal detection signal when a pattern is not detected.

The duty discriminating circuit 3 includes first to n-th pattern detecting circuits 2-1 to 2-n for n polyphase clocks.
And the duty of the received signal is determined based on the number of continuous normal detection signals among the n pattern detection results.

The duty value of the received signal determined by the duty determination circuit 3 is preferably encoded into a predetermined digital code and notified to the next stage circuit 4. In the line termination device, the circuit 4 receives the received AMI signal. A signal and a duty value are input, and a predetermined circuit operation is performed based on the duty value of the received signal waveform.

Referring to the timing waveform diagram of FIG.
The i-th pattern detection circuit that inputs the phase clock outputs an abnormality detection signal (that is, no pattern exists at the time of clock input), and the i-th pattern detection circuit that inputs the i-th phase clock to the j-th phase clock outputs the j-th pattern detection circuit. The normal detection signal is continuously output with respect to the received AMI signal up to the pattern detection circuit (that is, there is a pattern at the time of clock input), and the j + 1-th pattern detection circuit that inputs the (j + 1) th phase clock again becomes abnormal. Since the detection signal is output, the duty ratio (for example, (ji) / n) of the effective signal can be obtained.

In the above embodiment, the circuit for measuring the duty of the received signal in the line termination device has been described. However, the present invention is not limited to the above embodiment, and the pulse period of a general signal to be measured (pulse train) is not limited thereto. Of course, the present invention is also applied to a device for measuring the pulse duration for the pulse width.

[0017]

As described above, according to the present invention,
Since the duty is measured by the multi-phase clock, the duty can be measured without requiring a high-frequency oscillator. For this reason, the present invention is suitably used in a line terminating device for a selector of a circuit that performs different operations depending on the duty of a received signal.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a duty measurement circuit according to the present invention.

FIG. 2 is a timing waveform chart for explaining a determination result based on an AMI reception signal and a multiphase clock in one embodiment of the duty measurement circuit of the present invention.

[Explanation of symbols]

 Reference Signs List 1 polyphase clock generation circuit 2-1 to 2-n pattern detection circuit 3 duty discrimination circuit 4 next stage circuit 5 oscillator

Claims (4)

(57) [Claims] A duty measuring circuit in a receiving unit for receiving a signal encoded by an RZ code on a line in a digital line terminating device, wherein T is a period corresponding to one bit length of the received signal , , KT / n (where n is the resolution, k = 1,
A multi-phase clock generation circuit for generating and transmitting n multi-phase clocks each delayed by 2,..., N), and the multi-phase clock generated by the multi-phase clock generation circuit as inputs. Defined by n polyphase clocks
Detecting a logic level of the received RZ signal at the time, said logical relay
Sometimes normal detection signal level matches the predetermined value, double that output the sometimes abnormality detection signal mismatch
Receiving a number (n) of detection circuits; and an output result of the plurality of detection circuits with respect to the n multi-phase clocks, and a normal detection signal among the n detection results
Is continuously detected on the time axis m (where m ≦ n)
If the duty measuring circuit from this m the n, a duty determination circuit for encoding to determine the duty cycle of the received signal, comprising the. 2. A period of a signal to be measured is defined as T, and a predetermined phase (= kT / n, where k =
Clock generating means for generating and outputting a plurality of (n) clocks shifted by 1, 2,... N), and at a time determined by each of the plurality of clocks,
Whether the measured signal matches a predetermined value
Duty measuring circuit for detection means for whether or not the detection and determination means for determining a duty cycle of the signal under test based on a detection result of said detecting means with respect to said plurality of clock, comprising the. Wherein said detecting means, said type a single clock among the plurality of clock signal to be measured, on the basis of the clock signal, the pulse waveform of the signal under measurement, the
The period between the rise and fall of the pulse signal
To detect if it has a predetermined pulse duration .
A plurality of detecting means for calculating a ratio between a pulse duration and a pulse period of the signal under measurement based on detection results of the plurality of detecting means. The duty measurement circuit described. 4. A multi-phase clock having a phase delay obtained by equally dividing a time corresponding to one pulse period of the signal under measurement by a predetermined number (n). The duty measurement circuit according to claim 2, wherein the duty measurement circuit generates the duty measurement from a clock.