JPS62131637A - Timing jitter measuring system - Google Patents

Abstract

PURPOSE:To obtain the result of measuring representing the elapsed time of jitter quantity at every time slot by providing a storage means writing a data representing the time width decided depending on the quantity of phase jitter in a location represented by an address signal indicating a time slot number. CONSTITUTION:When a jitter measuring period is designated at the pulse leading of a set signal at the measurement, a clock pulse train of sampling signal appears in the transmission signal of an AND gate 2 for a pulse leading period in common to both a reference timing signal and a timing signal extracted from the output pulse being the object of measurement. A counter circuit 3 resets the result of count to zero at every leading of the pulse of the reference timing signal, counts the clock pulse of the transmission signal from the gate 2 and sends the data representing the count result to a bus. Further, a counter circuit 4 is reset by the pulse leading of the set signal, counts the pulse of the reference timing signal, generates the result of count representing the time slot number and sends it to a path as an address. A CPU 6 makes a memory circuit 5 write the data to a location shown in the address.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a timing jitter measurement method.

[Conventional technology]

In a digital communication system using pulse code modulation or the like, a self-timing extraction system is usually applied in which a timing signal is extracted from a pulse train received from a transmission path.

In this case, since a waveform encounter occurs or noise is added during transmission of the received pulse train, the phase of the extracted timing signal deviates from the original timing phase, resulting in timing jitter.

The conventional timing jitter measurement method is to compare the phases of the extracted timing signal and the reference timing signal, convert the phase difference between the two into voltage amplitude, and then pass it through a low-pass filter to obtain the effective value of the timing jitter. is used.

[Problem that the invention seeks to solve]

In the conventional timing jitter measurement method described above, what is obtained as a measurement result is an effective value that indicates the average value of the amount of jitter over a relatively long period of time. The problem is that it is not possible to know whether the data will be used, and the data is often insufficient for designing or evaluating communication systems and equipment.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing jitter measurement method that can obtain measurement results indicating the elapse of time in the amount of jitter for each time slot in order to solve the above-mentioned problems.

[Means for solving problems]

The measurement method of the present invention includes a logic gate that receives a reference timing No. 16 and a timing signal having phase jitter relative to the reference timing and generates a pulse having a time width determined according to the amount of phase jitter; a first timer that measures the time width of the pulse and generates data representing the measurement result; and a second timer that generates an address signal indicating a time slot number by counting the number of pulses at the reference timing. and storage means for writing the data at a location indicated by the address signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block N showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining its operation.

In FIG. 1, timing 100 is a timing signal extracted from a received pulse train of a communication device applied to a transmission path to be measured, and is sent to AND gate 1 together with a reference timing signal. The sampling signal is a clock pulse train having a predetermined frequency that is faster than the timing signal. The set No. 1- is a pulse for instructing the jitter measurement period. The sampling signal and the set signal are sent to the AND gate 2 along with the output signal of the AND gate 1.

The output signal of the AND gate 2 is sent to the counting input terminal of the counting circuit 3. A reference timing signal is applied to the reset terminal of the Mt number circuit 3. Further, a reference timing signal is applied to the counting input terminal of the ht number circuit 4, and a set signal is applied to the reset terminal.

Data indicating the counting results of the counting circuit 3 and the tr number string 4
The address number g indicating the counting result is sent to the bus connecting the processor (CPU) 6 and the memory circuit 5.

As shown in Fig. 2, when the jitter measurement period is specified by the pulse rising period of the set signal during measurement, the output signal of the AND gate 2 includes the timing extracted from the reference timing signal and the output pulse of the object to be measured. The clock pulse train of the sampling signal appears only during the pulse rising period common to the signal circle. The counting circuit 3 in FIG.
After resetting the counting result to zero every time the pulse of the reference timing signal rises, the clock pulse of the output signal of the AND gate 2 is counted, and data indicating the counting result is sent to the bus. Further, after being reset by the rising edge of the pulse of the set signal, the counting circuit 4 counts the pulses of the reference timing signal, generates a counting result indicating the number of the time slot, and sends it to the bus as an address. The CPU 6 controls the data and address of the counting circuit 3 immediately before being reset to the memory circuit 5, and writes the data to the location indicated by the address in the RAM (memory for both internal and external use) in the memory circuit 5. Cause data to be written. At the end of the preset jitter measurement period, the pulse of the set signal falls and the writing to the memory circuit 5 described above is completed. During this time, data indicating the time width of the pulse rising period of both the timing signal under test and the reference timing signal is sequentially written into the memory circuit 5 for each time slot. Since these data represent a time series that changes in accordance with the amount of jitter for each time slot, the CPU 6 reads this data series from the memory circuit 5 and processes it using, for example, a digital signal processing algorithm).
By performing spectral decomposition of jitter, it is possible to obtain desired data for designing or evaluating communication systems and equipment.

Note that if an exclusive OR gate is used in place of the AND gate 1 in this embodiment (FIG. 1), the leading edge of the pulse of the timing signal under test and the reference timing signal and the A signal is obtained in which the clock pulses of the sampling signal appear only during each mismatch period of the trailing edge.

Therefore, in this case, it is clear that a data sequence indicating the amount of jitter at the pulse MiT edge and trailing edge of the timing signal is obtained for each time slot (not shown).

〔Effect of the invention〕

As explained above, the present invention has the effect of realizing a timing jitter measurement method that can obtain measurement results that indicate the elapsed time of jitter in each time slot as a digital value, especially when the measurement results are analyzed by a processor. The effect is remarkable when applied to

[Brief explanation of drawings]

1 and 2 are a block diagram and a timing diagram, respectively, showing one embodiment of the present invention. 1.2......AND gate, 3,4...
Counting circuit, memory circuit, 6...
Processor (CPU). Figure 1

Claims (1)

[Claims] A logic gate that receives a reference timing signal and a timing signal having phase jitter relative to the reference timing signal and generates a pulse having a time width determined according to the amount of the phase jitter, and measures the time width of the pulse generated by the logic gate. a first timer for generating data indicating the measurement result; a second timer for counting pulses at the reference timing and generating an address signal indicating a time slot number; and a location indicated by the address signal. and storage means for writing the data into the timing jitter measuring method.