JPH0378586B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to the number of times a signal having binary voltage levels represented by "H" and "L" changes from level "H" to level "L" (hereinafter referred to as falling); The present invention also relates to a pulse counting device that counts the number of times the level changes from level "L" to level "H" (hereinafter referred to as rising), and particularly relates to processing when the waveform of the input binary signal is a narrow pulse shape.

Figure 1 is a block diagram showing an example of a pulse counting device configured using a microcomputer.
1 and 2 are signal input terminals, 3 is a photocoupler, 4 and 5
is a resistor, 6 is an inverter with a binarization function, and 7 is a resistor.
is a microcomputer, 7a is an input/output unit (hereinafter abbreviated as I/O), and 7b is a processor unit (hereinafter abbreviated as I/O).
7c is a memory.

FIG. 2 is a flowchart showing the operation of the apparatus shown in FIG. 1, showing each step in counting the number of falling points of a signal (points of change from level "H" to level "L"). Using a sampling pulse with a short repetition period compared to the pulse width of the output signal of the inverter 6, the CPU
In step 7b, the level of the input signal at the time of the sampling pulse is measured and written into the memory (step 9). Next, compare the contents of the current memory with the contents of the previous memory (explained later) (step 1).
0), if they match, the process moves to step 13 and the contents of the current memory are written to the previous memory. In the initial state, it is necessary to perform control so that step 10 always returns YES. That is, the previous memory is a register that holds the contents of the current memory one sampling pulse ago. If step 10 is NO,
And when the contents of the memory indicate the level "L" this time in step 11, the input signal changes from "H" to "L".
This indicates that the number has fallen, so the number 1 is stored in the counting memory.
is added (step 12), and the process of step 13 is performed. At the place where NEXT is written, the process waits for the next sampling pulse to arrive, and when the next sampling pulse arrives, it starts from step 9. Also,
If NO in step 11, it indicates the rising point, so proceed to step 13 to proceed to NEXT.

Figure 3 is a waveform diagram showing the relationship between the input signal and the sampling pulse, where a and c in Figure 3 are the input signals, b is the sampling pulse, and d is the falling edge of the input signal shown in c in Figure 3. Points 31b, 31d,
The output logic of the flip-flop whose logic is inverted when triggered by 31f and 31h is shown. For the input signal shown in Figure 3a, the sampling pulse 30
Between a and 30b, between 30c and 30d, 30e,
30f, NO is determined in step 10 of FIG. 2, YES is determined in step 11, and falling points are counted in step 12. However, for the input signal shown in FIG. 3b, the period of the sampling pulse is equal to the pulse of the input signal. Since it is longer than the width, there is no sampling pulse within the pulse width of the input signal, and therefore some of the falling points 31b, 31d, 31f, and 31h are omitted in counting. In such a case, the third
The waveform in Figure 3 d is generated from the waveform in Figure c, and 32
What is necessary is to count b, 32d, 32f, and 32h.

FIG. 4 is a block diagram showing another example of the conventional device, in which the same reference numerals as in FIG. 1 indicate the same parts, and 20 is a T.
It is a flip-flop in shape. When the output of the inverter 6 is as shown in FIG. 3c, the logic at the output terminal Q of the flip-flop 20 is as shown in FIG. 3d. If this is input and step 11 in FIG. 2 is omitted, 32b, It is clear that points 32d, 32f, and 32h can be detected.

However, assuming that a power outage occurs once in the circuit shown in Figure 4 and then the power outage is restored, the microcomputer 7 has measures against power outages, and for example, the data immediately before the power outage is saved to nonvolatile memory. After the power is restored, the evacuated data is returned to the original register, but the flip-flop 20
Since it is uncertain what the output logic will be, the fourth
The circuit shown in the figure has a drawback in that depending on the state of the flip-flop 20, a counting error of one pulse may occur.

The present invention was made to eliminate the above-mentioned drawbacks of conventional devices, and an object of the present invention is to provide a pulse counting device that does not generate pulse counting errors between the occurrence of a power outage and the restoration of a power outage.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 is a waveform diagram showing signal waveforms including power outage and power outage recovery, where FIG. 5 a shows the input signal waveform, and FIG.
It shows the output of a flip-flop whose output logic is inverted when triggered at 0c, 50f, and 50g.
d and 51d indicate the occurrence of a power outage, and 50e and 51g indicate the power outage recovery point. FIG. 6 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 4 indicate the same parts, and 21 is a power failure detection circuit. Power outage detection circuit 2
1 and the processing at the time of power outage and power outage recovery are generally known and will not be described here, but it is assumed that the microcomputer 7 is equipped with such a processing device.

FIG. 7 is a flow diagram showing the operation of FIG.
-45 indicate program steps, and compared with FIG. 2, 9 and 41, 10 and 42, 12 and 4
3, 13 and 44 correspond, step 11 is omitted and steps 40 and 45 are added. Therefore, steps 41 to 44 are executed in the same way as the circuit in FIG. 4 except for recovery from a power outage, but step 40
If YES, the logic of the input signal sampled by the sampling pulse at that time is directly input to the previous memory. That is, when the power is restored at 51e, the output logic of the flip-flop 20 at the sampling pulse immediately after 51e is input to the previous memory (step 45), regardless of the contents of the previous memory. Since the output logic of the flip-flop 20 is input to the memory this time (step 41), no counting error will occur no matter how the output logic of the flip-flop 20 is set upon recovery from a power failure.

In the above embodiment, the case where there is one input signal circuit has been described, but in the case of a plurality of input signal circuits, the same procedure may be performed for each circuit. Furthermore, if noise is superimposed on the signal waveform input to the I/O 7a, the input signal is processed as having the corresponding logic only when the same logic continues for multiple sampling pulses. However, the present invention can also be used in such cases.

Although FIG. 6 shows an embodiment using the microcomputer 7, it is also easy to construct a dedicated circuit for executing the operations shown in FIG.

As described above, according to the present invention, it is possible to provide a pulse counting device that does not cause erroneous counts due to power outage and power restoration even when counting pulses in a narrow pulse-like binary signal. .

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional pulse counting device configured using a microcomputer, Fig. 2 is a flow diagram showing the operation of the device shown in Fig. 1, and Fig. 3 is a block diagram showing the operation of the device shown in Fig. 1. FIG. 4 is a block diagram showing another example of the conventional device, FIG. 5 is a waveform diagram showing signal waveforms including power outage and power recovery, and FIG. 6 is a waveform diagram showing an embodiment of the present invention. The block diagram shown in FIG. 7 is a flow diagram showing the operation of FIG. 6. 1, 2...Signal input terminal, 3...Photocoupler,
6...Inverter, 7...Microcomputer, 7a...I/O, 7b...CPU, 7c...
Memory, 20...T-type flip-flop, 21...
...Power failure detection circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a pulse counting device that counts the number of times a signal having a binary voltage level inverts the voltage level and becomes a predetermined voltage level, the above signal is input, and the voltage level is inverted and becomes the predetermined voltage level. A flip-flop whose output logic is inverted when triggered by a signal change at a point in time; a current memory that samples the output logic of the flip-flop using a sampling pulse having a predetermined period and stores the logic at the latest sampling point; A value of 1 is added each time the previous memory input at a time one sampling cycle later than the current memory content and the current memory content have a different logic from the previous memory content. a counter, and means for saving the contents of the current memory, the previous memory, and the counter to a nonvolatile memory when the device is out of power, and setting the contents of the current memory, the previous memory, and the counter from the nonvolatile memory to the current memory, the previous memory, and the counter, respectively, when the power is restored. , means for directly inputting only the logic of the input signal sampled by the first sampling pulse after restoration of the power outage to the previous memory.