JP2613916B2 - Data aperiodic readout circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for detecting the presence or absence of a pulse signal generated aperiodically in a digital circuit and reading data aperiodically.

[Conventional technology]

In a digital circuit, a fault in the digital circuit, an alarm signal such as a data error is a non-periodic pulse signal, and therefore, a conventional method for detecting the alarm signal includes a method using a signal extension circuit, There was a way to use flip-flops.

[Problems to be solved by the invention]

FIG. 4 shows a circuit in which a signal extending circuit is used in the above method. In the figure, 1 is a signal stretching circuit for inputting a pulse signal a1, 2 is an OR circuit for ORing the pulse signal a1 and the output signal a2 of the signal stretching circuit 1, and 3 is a signal data reading circuit. Flip-flop, T1 is an input terminal of pulse signal a1, T2 is an input terminal of clock a3 for reading timing of signal data of flip-flop 3, T3
Is an output terminal for outputting pulse presence data a4.

Next, the operation of the circuit of FIG. 4 will be described with reference to FIG. FIG. 5 (c) shows the output signal a2 of the signal stretching circuit 1 when the aperiodic pulse signal a1 shown in FIG. 5 (b) is applied to the input terminal T1. As can be seen from FIG. 5 (c), the signal extending circuit 1 is a circuit for extending the signal for one pulse signal input for a certain period of time, and the signal a3 is used as a reset of the signal extending circuit 1. You.

The period t1 in FIG. 5A is one pulse signal for one pulse signal.
This shows a case where data reading has been performed twice. Data reading is performed at the rising edge of the first clock a3 shown in FIG. A period t2 indicates a case where the pulse signal a1 cannot be detected by the signal stretching circuit 1 because the pulse signal a1 is generated while the reset pulse a3 of the signal stretching circuit 1 is being input. In the period t3, the pulse signal a1 is extended for a certain period of time by the signal stretching circuit 1 for one pulse signal a1 as shown in FIG.
This indicates a case where detection was not possible due to delay in reading a2. A period t4 shows a case where one pulse signal a1 continues for a long time. As described above, in the circuit of FIG.
When the states of t2 and t3 occur, there is a disadvantage that the pulse signal cannot be detected.

FIG. 6 shows a circuit in which a flip-flop is used in the above method. In the figure, 4 to 6 and 8 are flip-flops, 7 is an OR circuit, T4 is an input terminal of the pulse signal b1, T5 is an input terminal of a read signal b5 for reading data detected from the pulse signal b1, and T6 is a read terminal. This is an output terminal of the detection data b6 output by the input of the signal b5.

Next, the operation of the circuit of FIG. 6 will be described with reference to FIG. When the pulse signal b1 shown in FIG. 7 (b) is input to the terminal T4 in FIG. 6 and the read signal b5 in FIG. 7 (f) is input to the terminal T5 in FIG. 6, the terminal T6 in FIG. FIG. 7 (g) shows the obtained detection data b6. Period of Fig. 7 (a)
t1 indicates a case where data reading is performed during a period in which the pulse signal b1 is not generated. A period t2 is a period in which the pulse signal b1 is generated, and shows a case where data reading is performed. period
t3 indicates that data is read at the same time as the occurrence of the pulse signal b1, and the output data b2 and b6 (see FIGS. 7 (c) and 7 (g)) are undefined.
A period t4 shows a case where the width of the pulse signal b1 is long. The circuit shown in FIG. 6 has a drawback that when the state of the period t3 occurs, the data to be detected is undefined. The signals b3 and b4 in FIGS. 7D and 7E are output signals of the flip-flop 6.

[Means for solving the problem]

In order to solve such a problem, a data aperiodic readout circuit according to the present invention has two flip-flops for inputting a pulse signal generated aperiodically and detecting the presence or absence of the pulse signal, A pulse signal detection circuit comprising an OR circuit for taking a logical sum of the Q outputs and outputting a pulse presence / absence signal indicating the presence / absence of the pulse signal; a pulse presence / absence read request signal for aperiodically reading the pulse presence / absence signal; A sampling clock for detecting a pulse presence / absence read request signal is input, and a pulse presence / absence read signal in which the phase of the pulse presence / absence read request signal is changed in accordance with the sampling clock, and every other pulse presence / absence read request signal A reset signal for alternately resetting the two flip-flops in synchronization with the reset signal. A signal generation circuit, and a data read circuit that receives the pulse presence / absence signal output by the pulse signal detection circuit and the pulse presence / absence read signal output by the reset signal generation circuit, and reads a pulse presence / absence signal. Things.

[Action]

In the data aperiodic readout circuit according to the present invention, detection data indicating the presence or absence of a pulse signal can be read out aperiodically.

〔Example〕

The data aperiodic readout circuit according to the present invention employs a flip-flop for detecting a pulse signal generated aperiodically in order to improve the disadvantage of a circuit using two flip-flops in the method described in the section of [Prior Art]. The flip-flop to be used is alternately switched by synchronizing the reset timing with every other pulse presence / absence read request signal, and the data can be latched in both flip-flops at the moment of reading data with the pulse presence / absence read request signal It has the feature of being in a state.

Next, a data aperiodic readout circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data aperiodic readout circuit according to the present invention classified by function, and FIG. 2 is a circuit diagram showing the embodiment of FIG. 1 and 2, 10 is a pulse signal detection circuit, 20 is a reset signal generation circuit, 30 is a data read circuit, T10, T20, T21 are input terminals, T30 is an output terminal, 11, 12, and 2.
1, 22, 24 and 26 are flip-flops, 13 is an OR circuit, 23 is an AND circuit, 25 is an inverter, 27 is a NAND circuit, and 28 is an OR circuit.

FIG. 3 is a time chart for explaining the operation of the circuit of FIG. The operation of the embodiment of FIG. 2 will be described with reference to FIG. Third to pulse signal input terminal T10 in FIG.
The pulse signal a shown in FIG. 3A is inputted, the pulse presence read request signal d shown in FIG. 3D is inputted to the pulse presence read request signal input terminal T20 shown in FIG. 2, and the sampling clock input terminal shown in FIG. The sampling clock c of FIG. 3 (c) is input to T21, and the pulse presence / absence data output terminal T3 of FIG.
From 0, the pulse presence / absence data 1 of FIG. 3 (1) is output. A pulse signal a shown in FIG. 3 (a) is input to a terminal T10, a pulse signal is detected by a pulse signal detection circuit 10, a pulse presence / absence signal b is output, and a pulse presence / absence read request signal d is input to a terminal T20. The pulse presence / absence read request signal d is detected by the sampling clock c inputted at the terminal T21, and becomes a pulse presence / absence read signal e shown in FIG. 3 (e). Further, the signals are converted into signals f-k shown in FIGS. 3 (f)-(k) by gates, flip-flops and the like. Signals j and k shown in FIGS. 3 (j) and 3 (k) are signals from the reset signal generation circuit 20 to the pulse signal detection circuit 10, and the pulse signals are detected at the timings shown in FIGS. 3 (j) and 3 (k). By setting the two flip-flops used in the circuit 10 to the latchable state, it is possible to detect a pulse signal generated aperiodically regardless of the timing of the pulse presence / absence read request signal shown in FIG. I understand.

〔The invention's effect〕

As described above, the present invention provides a pulse signal detection circuit that outputs a pulse presence / absence signal, a reset signal generation circuit that outputs a signal that resets a pulse presence / absence signal, and a pulse presence / absence read signal that changes the phase of a pulse presence / absence read request signal. Providing a circuit and a data readout circuit for inputting a pulse presence / absence signal and a pulse presence / absence readout signal and reading out a pulse presence / absence signal enables non-periodically reading out detection data indicating the presence / absence of a pulse signal, The pulse signal generated aperiodically can be detected without being restricted by the timing of the pulse presence / absence read request signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a data aperiodic readout circuit according to the present invention, FIG. 2 is a circuit diagram showing the circuit of FIG. 1, and FIG. 3 explains the operation of the circuit of FIG. FIG. 4 is a circuit diagram showing an example of a conventional data aperiodic readout circuit, FIG. 5 is a time chart for explaining the operation of the circuit of FIG. 4, and FIG. FIG. 7 is a circuit diagram showing another example of the periodic reading circuit, and FIG.
6 is a time chart for explaining the operation of the circuit shown in FIG. 10 pulse signal detection circuit, 20 reset signal generation circuit, 30 data readout circuit, 40 flip-flop, T10, T20, T21 input terminal, T30 output terminal 11, 1
2, 21, 22, 24, 26 ... flip-flop, 13, 28 ... OR circuit, 23 ... AND circuit, 25 ... inverter, 27 ... NAND circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-142913 (JP, A) JP-A-61-230516 (JP, A) JP-A-56-141640 (JP, A)

Claims (1)

(57) [Claims] An input of a pulse signal generated in an aperiodic manner, two flip-flops for detecting the presence or absence of the pulse signal, and a pulse representing a logical OR of the Q output of the flip-flop to indicate the presence or absence of the pulse signal A pulse signal detection circuit including an OR circuit that outputs a presence / absence signal, a pulse presence / absence read request signal for aperiodically reading the pulse presence / absence signal, and a sampling lock for detecting the pulse presence / absence read request signal are input. And a reset for alternately resetting the two flip-flops in synchronization with every other pulse presence / absence read request signal in which the phase of the pulse presence / absence read request signal is changed in accordance with the sampling lock. A reset signal generating circuit for outputting a signal and the pulse output from the pulse signal detecting circuit And said pulse existence read signal presence signal and said reset signal generating circuit outputs as input, data aperiodic readout circuit that includes a data reading circuit for reading the pulse existence signal.