JP3364943B2 - Clock skew correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION The present invention relates to a digital VTR and the like.
Clock skew applied to digital signal recording / reproducing device
-Regarding the correction circuit, in particular, the clock correction after SYNC detection
A clock skew correction circuit suitable for a positive circuit
I do. [0002] 2. Description of the Related Art Clock skew is applied to a SYNC detector.
The clock to the SYNC pattern detected
Occurs sometimes. In the SYNC detector, the input data
Search for SYNC pattern while shifting
When this is detected, the phase synchro
Generate a lock. As a result, the input data
Causes the clock phase to shift by that amount.
You. When pulling the clock into this new phase,
A new clock is generated, resulting in clock skew. clock
Digital circuit malfunctions if it contains skew
It is necessary to correct the skew because there is a fear. this
Must be corrected for constrictions in the data
No. [0003] Conventional techniques for correcting clock skew
As a technique, a method using a FIFO memory is known.
This method will be described with reference to FIGS. [0004] In FIG.
FIFO memory of synchronous operation, 22 is read reset signal
Signal generation circuit, 23 is a data input terminal, 24 is a data output
Terminal, 25 is a write clock input terminal, 26 is SYN
C signal input terminal, 27 is a read clock input terminal
You. FIG. 3 shows the clock skew correction circuit of FIG.
It is a timing chart which shows an operation | movement, (a) enters into 25.
Write clock with skew applied, (b) 23
Input data to be input to SY, (c) is SY input to 26
NC signal, (d) does not include skew input to 27
Read clock, (e) is read output from 22
Reset signal, (f) is output data output from 24
is there. The FIFO memory 21 stores a SYNC signal (c)
Becomes low level, the internal write address counter
Is reset, and the input data (b) is written to address 0.
You. Thereafter, the write address counter will be
The input data is incremented by one for each lock (a).
(b) is sequentially written into the FIFO memory 21. reading
Similarly, on the output side, the read reset signal (e) is set to low level.
Resets the internal read address counter
Then, the output data (f) is read from address 0. this
After that, the read address counter reads the read clock
(d) is incremented by one for each output data.
Is read from the FIFO memory 21. Here,
From FIFO memory 21 with clock (d) not including
Because data is being read, the output data (f) is
And the clock skew is corrected. [0007] SUMMARY OF THE INVENTION The above conventional clocks
In the cue correction circuit, the FIFO memory 21 and the read resource
The set signal generation circuit 22 is required, and the circuit scale is large.
There was a problem of becoming. An object of the present invention is to provide a small clock
It is to provide a skew correction circuit. [0009] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In addition, the present invention uses parallel data in synchronization with the input clock.
And a means for dividing the clock.
The parallel data input to the register is serial
It is assumed that the data has been converted from serial to parallel,
The means for dividing the clock is a clock synchronized with the serial data.
Outputs the lock divided clock, and
The lock is the divided clock.Also solved the above problems
Input data is serial data.
Detects SYNC code of real data and outputs SYNC signal
And the above serial data
SYNC detector that outputs parallel data that has been converted
And the input clock is a clock synchronized with the serial data.
Clock whose phase has been shifted by half a cycle (hereinafter “half
The period shift clock)).
Divides the clock to the same as the parallel data output cycle
Outputs periodic clock (hereinafter referred to as “divided clock”)
Means (hereinafter referred to as "frequency dividing means") and the frequency dividing means
The divided clock to be output and the SYNC detector output
The parallel data to be input and the divided clock
A first register for inputting and outputting the parallel data in synchronization with the first register
And the frequency-divided clock output by the frequency-dividing means.
The SYNC signal output from the SYNC detector is input and
And the parallel data is synchronized with the divided clock.
A second register for inputting and outputting, the first register
Is the rising edge of the input divided clock.
To capture the parallel data input and hold it
The second register stores the input
At the rise of the peripheral clock, the input SYNC signal
No. is captured, and this is retained and output.
The parallel data and the SYNC signal are clocked
If skew is included, the first register and the skew
A second register stores the parallel data and the S
The YNC signal is output in synchronization with the frequency-divided clock.
Therefore, clock skew can be corrected. [0010] [Function] To correct clock skew, input data
Data on a clock with the same frequency
Can be changed. However, input data and new cross
If the clocks are asynchronous, the phase difference may approach zero.
At this time, data cannot be
It may be. Therefore, in the present invention, input to the SYNC detector is performed.
Divide clock synchronized with serial data before input
And a new clock. Therefore, this frequency division
Locks are synchronized with input data and include skew
Not in. Also, the amount of clock shift caused by skew
Is the unit of one cycle of the clock synchronized with the serial data
Clocks synchronized with the input data when dividing.
Clock half cycle synchronized with serial data for clock
By shifting the phase, the register always
Can be inserted. As described above, the clock skew is corrected.
You can see that. [0013] 1 shows a clock skew correction circuit according to the present invention.
1 is a first embodiment of a road. In FIG. 1, 1 is a D-type free
Flip-flop circuit, 2 for data input terminal, 3 for data output
The input terminal 4 is a clock input terminal, and the reference numeral 5 is a frequency dividing circuit. FIG. 4 shows the clock skew correction circuit of FIG.
6 is a timing chart showing an operation.Figure 1 shows
Data that is not input to the data input terminal 2 in FIG.
Is the SYNC signal detection and serial parameter of serial data.
Parallel data output by the SYNC detector that performs the real conversion
It is.In FIG. 4, (a) isOf FIG.Data input terminal
Entered in 2Serial-parallel convertedParallel de
Data, (b)A SYNC signal output by the SYNC detector,
(c) isOf FIG.Clock input terminal4Serial input to
Clock synchronized with data, (d)Of FIG.Divider 5
(E) Data output terminal3Out of
This is the data to be input.4, FIG.D type free
The flip-flop circuit 1 is turned on at the rising edge of the clock (d).
Input force data (a) and output data (e).In FIG.
AndClock (d) is divided by clock (c)
Since the frequency is the same as clock (b), clock (d)
Does not include skew and is synchronized with clock (a). Ma
WasIn FIG.The phase is shifted by half a cycle of clock (c).
BecauseOf FIG.D-type flip-flop circuit 1 has an input
Data (a) can always be captured. Therefore, the output
Data (e) is synchronized with clock (d) that does not include skew.
This means that the clock skew has been corrected. [0015]In FIG.Raw skew of data (a)
Data P0 during the same period as one cycle of clock (d)
Short, so it can be captured by the D-type flip-flop circuit 1.
Sometimes it does not. But what about clock skew
Data P0 is invalid because of the error
There are many. In particular, clock skew generated by the SYNC detector
-P0 is erroneous data, and there is no problem if P0 is lost
There is no. According to this embodiment, clock skew correction is performed.
This has the effect of reducing the circuit scale of the circuit. FIG. 5 shows a SYNC detection circuit according to the present invention.
This is an example. In FIG.1 is a D-type flip-flop
3 is a data output terminal, 4 is a clock input terminal,
5 is a frequency dividing circuit,51 is a clock skew according to the present invention.Supplement
CorrectCircuit, 52 is a SYNC detector, 53 is a D-type flip-flop
Circuit 54, a data input terminal 54, and a SYNC signal 55.
Signal output terminal. The SYNC detector 52 receives the data
Input from terminal 54CerealSYNC pattern from data
OrofdetectionAnd serial parallel of input serial data
Do the conversion, SYNC signalAnd SSynchronized with YNC signal
parallelOutput data. Output of SYNC detector 52
The parallel data is input to the clock skew correction circuit 51.
To remove skew. SYNC detector 52
SYNC signal output from the D-type flip-flop
The circuit 53 causes the clock skew correction circuit 51 to
Data is delayed by the same time
The signal is output from the signal output terminal 55. According to this embodiment, the circuit of the SYNC detection circuit is used.
This has the effect of reducing the road scale. [0019] According to the present invention, the clock can be reduced by a small circuit.
A deskew correction circuit can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a first embodiment of a clock skew correction circuit according to the present invention.
FIG. FIG. 2 is a circuit diagram of a clock skew correction circuit according to the related art. FIG. 3 is a timing chart of FIG. 2; FIG. 4 is a timing chart of FIG. FIG. 5 is a diagram illustrating a clock scan of a SYNC detection circuit according to the present invention;
FIG. 3 is a block diagram of an embodiment of a circuit for correcting a view. [Description of Signs] 1 ... D-type flip-flop circuit, 2 ... data input terminal,
3 data output terminal, 4 clock input terminal, 5 frequency divider circuit, 21 FIFO memory for asynchronous read / write operation
Memory, 22: Read reset signal, 23: Data input
Terminal, 24: data output terminal, 25: write clock
Input terminal, 26: SYNC signal input terminal, 27: reading
Clock input terminal, 51 clock skew correction
Road, 52: SYNC detection circuit, 53: D-type flip-flop
Circuit, 54 ... data input terminal, 55 ... SYNC signal
Output terminal.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/10

Claims (1)

(57) [Claims 1] The input data is serial data, and the SYNC signal of the serial data is detected and the SYNC signal is detected.
Output and the serial data
SYNC detection to output parallel data after parallel conversion
Output and an input clock are clocks synchronized with the serial data.
Is a clock whose phase is shifted by a half cycle (hereinafter referred to as “half cycle”).
Shift clock)).
Frequency and the same cycle as the parallel data output cycle
Hand that outputs clock (hereinafter referred to as "divided clock")
Stage (hereinafter referred to as "frequency dividing means"), the frequency-divided clock output by the frequency dividing means and the SYN
The parallel data output from the C detector is used as an input.
Input / output the parallel data in synchronization with the divided clock
A first register, the divided clock output from the frequency dividing means, and the SYN
Receiving the SYNC signal output from the C detector as an input,
The parallel data is input / output in synchronization with the divided clock.
And a first register, wherein the first register has the input of the frequency-divided clock.
At the rise, input of the parallel data is taken.
Inclusive, which was holding the output, year second register, the frequency division clock input
At the rising edge, capture the input SYNC signal
And the parallel data and the SYNC signal are clocked.
If skew is included, the first register and the skew
A second register stores the parallel data and the S
The YNC signal is output in synchronization with the frequency-divided clock.
Clock skew can be compensated for
Lock skew correction circuit.