JP3031554B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an information processing apparatus for processing image data, and more particularly to an image processing apparatus for performing high-speed image processing, in which an external clock signal and a dot clock signal are asynchronously input. It is an object of the present invention to provide an image processing apparatus which reduces a data conversion error due to a timing shift at the time of parallel / serial conversion processing of pixel data generated based on the above, and reduces screen disturbance. Parallel / serial data conversion means for taking in parallel based on an external clock signal, converting the plurality of pixel data into serial data, and outputting the serial data in synchronization with a first clock signal asynchronous with the external clock signal In the image processing apparatus provided with, the external clock signal is input, the external clock signal and A second clock signal having the same period and synchronized with the first clock signal is generated, and the second clock signal is output to the parallel / serial conversion means as a timing for taking in the plurality of pixel data. A synchronization circuit that delays the rise of the second clock signal when the rise of the external clock signal and the rise of the first clock signal are close to each other within a predetermined time; After delaying the rise, only a plurality of pixel data taken in by the parallel / serial conversion means are serially output in synchronization with the first clock signal.

[Industrial applications]

The present invention relates to an information processing apparatus that processes image data, and more particularly to an image processing apparatus that performs high-speed image processing.

An image memory for storing image data (pixel data) requires a large capacity, and usually a DRAM or the like is used. However, since the reading speed of these image memories is lower than the drawing speed, it is not possible to directly read pixel data from the image memory and perform drawing. Therefore,
As shown in FIG. 4, for example, five pieces of pixel data (A, B, C, D, and E) are simultaneously read out in parallel from the image memory M, and are parallel / serial converted at high speed by a parallel / serial converter. In this case, a method of performing a drawing process is used. Thereby, as shown in FIG.
The pixel data A, B, C, D, and E that have been serially converted are displayed on the display screen at high speed.

In this case, it is necessary to match the timing of capturing a plurality of pixel data in parallel with the timing of display by performing parallel / serial conversion of the captured pixel data.

[Conventional technology]

Conventionally, as shown in FIG. 6, when five pieces of pixel data are taken in at one time, if the drawing timing, that is, the timing of performing parallel / serial conversion is t (sec), a plurality of pixel data can be read in parallel. It was necessary to synchronize the fetch timing T to fetch T = 5 · t (sec). That is, it is necessary to synchronize the external clock signal for capturing data in the image memory (hereinafter, external clock signal) and the high-speed clock signal for drawing (hereinafter, referred to as dot clock signal).

[Problems to be solved by the invention]

Normally, the period of the dot clock signal is specific to the device, but since the external clock signal is set by the user according to the purpose, the two are not synchronized, and the user synchronizes as necessary. Needed.

Therefore, as shown in FIG. 7, when the rising edge R of the external clock signal exists in the region w, is the rising edge r of the dot clock signal one clock signal after the rising edge R of the external clock signal? , One clock signal before the rise R, or an indeterminate state.

More specifically, as shown in FIG. 8 (a),
Although five dot clock signals should exist in one external clock signal, in the case shown in FIG. 8B, the external clock signal and the dot clock signal are not synchronized. It is possible that the rising edge of the external clock signal exists within the hold and setup time of the dot clock signal and is recognized as six dot clock signals. In such a case, if the display is to be performed as it is, the parallel data of the pixel data A, B, C, D, and E fetched from the image memory are converted into serial data, for example, A, B, C, D, It becomes six pixel data of E and X (X is indefinite data), which causes color misregistration at the stage of drawing and disturbance of the screen as noise.

Therefore, the present invention reduces an error in data conversion due to a timing shift at the time of parallel / serial conversion processing of pixel data, which occurs due to asynchronous input of an external clock signal and a dot clock signal. It is an object of the present invention to provide an image processing apparatus for reducing the number of images.

[Means for solving the problem]

In view of the above problem, the present invention takes in a plurality of pixel data (A to E) in parallel based on an external clock signal (LD), converts the plurality of pixel data into serial data, and converts the serial data into the external data. In an image processing apparatus provided with a parallel / serial conversion means (13) for outputting in synchronization with a first clock signal (DCK) which is asynchronous with a clock signal (LD), the external clock signal (LD) is inputted, A second clock signal (LDL) having the same period as the external clock signal (LD) and synchronized with the first clock signal (DCK) is generated, and the second clock signal (L
DL) as the timing for taking in the plurality of pixel data (A to E).
3), and when the rising of the external clock signal (LD) and the rising of the first clock signal (DCK) approach within a predetermined time, the second clock signal (LD) is output.
L) has a synchronous circuit (1) for delaying the rise, and after delaying the rise of the second clock signal (LDL),
Only the plurality of pixel data (A to E) taken in the parallel / serial conversion means (13) are serially output in synchronization with the first clock signal (DCK).

[Action]

Since the present invention is configured as described above, the parallel / serial conversion means (13) outputs the external clock signal (L
In place of D), parallel / serial conversion is performed based on the second clock signal (LDL) generated by the second clock signal generation means (3), and the external clock signal (LD) and the first clock signal (LD) are converted. DCK) is deviated by a predetermined value or more, the second means is used by the correction means (2).
The clock signal (LDL) is corrected and the data (A, B,
By controlling the capture of C, D, and E), the influence on serial data processing can be reduced.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

 FIG. 1 shows a block diagram of an embodiment of the present invention.

The synchronization circuit 1 detects a timing shift between the external clock signal LD and the dot clock signal DCK, and outputs a shift detection signal CR for correcting the timing shift, and the external clock signal LD and the dot clock signal DCK. If there is no timing deviation, an internal clock signal LDL synchronized with the dot clock signal DCK is generated in the same cycle as the external clock signal, and if there is a timing deviation, the internal clock signal An internal synchronization circuit 3 for generating a clock signal LDL.

The timing shift detection circuit 2 includes a first 1D flip-flop circuit 4 for outputting an external clock signal the first output signals S ₁ as input signals LD and the dot clock signal DCK each data terminal D ₁ and a clock terminal CK from the Q terminal, No.
1D the first output signal S ₁ and the 2D flip-flop circuit 5 for outputting a dot clock signal DCK data terminal D ₁ and the input signal and to the second output signal S ₂ of the clock terminal CK from the terminal each of the flip-flop circuit 4, 1st output signal
Using S ₁ , the second output signal S ₂ and a fourth output S ₄ signal described later as input signals, NAND (negation of logical product) is performed, and the result is converted to a third signal.
A first 1NAND circuit for the output signal S _3, the result shift detection signal takes the NAND of the third output signal S ₃ and the initialization signal INIT
The circuit includes a second NAND circuit 7 serving as a CR and a buffer circuit 8.

The internal synchronizing circuit 3 includes an inverted internal clock signal XLD described later.
L, and the 3D flip-flop circuit 9 to the seventh output signal S ₇ and the dot clock signal DCK respective data terminals D _1, D ₂ and the fourth output signal S ₄ as an input signal of the clock terminal CK and outputs from the Q terminal, the fourth output signal S ₄ and the dot clock signal DCK each data terminal D ₁ and a clock terminal C
A fifth output signal S ₅ as an input signal K and the 4D flip-flop circuit 10 to be output from the Q terminal, the fourth output signal S _4, the fifth
Seventh output signal S ₇ output signals S ₅ and the dot clock signal DCK are respectively inverted signals of the data terminal D _1, D ₂ and a clock terminal as an input signal CK sixth output signal S ₆ and the sixth output signal S ₆ A fifth D flip-flop circuit 11 which outputs the same from a Q terminal and a terminal, respectively, and a sixth output signal S ₆ , an inverted internal clock signal XLDL and a dot clock signal DCK, which will be described later, to data terminals D ₁ and D ₂ and a clock terminal C, respectively.
The internal clock signal LDL and the inverted internal clock signal XLDL which is the inverted signal of the internal clock signal LDL as the input signal of K
And a sixth D flip-flop circuit 12 that outputs the same from a Q terminal and a terminal, respectively.

 Next, the basic operation will be described.

The timing shift detection circuit 2 always outputs an external clock signal.
If a deviation between the LD and the dot clock signal DCK is detected, and a timing deviation of a predetermined value or more between the external clock signal LD and the dot clock signal DCK is not detected, the deviation detection signal CR is not output. At this time, the internal synchronization circuit 3
Operates independently of the timing shift detection circuit 2 and outputs an internal clock signal LDL synchronized with the dot clock signal DCK at the same cycle as the external clock signal LD from the Q terminal of the sixth flip-flop circuit 12. Will be.

On the other hand, the external clock signal LD and the dot clock signal
When a timing shift of DCK is detected, the shift detection signal CR is output from the timing shift detection circuit 2, and the internal clock signal LDL, which is the output signal of the sixth D flip-flop circuit 12, is forced to rise. It will be delayed and will start up when the deviation is no longer detected.

FIG. 2 shows a block diagram of an example of the parallel / serial conversion circuit.

The parallel / serial conversion circuit 13 includes five D flip-flop circuits 14, 15, 16, 17, and 18 connected in series.

Each of the flip-flop circuits 14, 15, 16, 17, 18 captures pixel data A, B, C, D, and E at the timing of the internal clock LDL, and outputs a dot clock signal DC.
With K, the data is sequentially output as serial data from the output terminal Q of the D flip-flop circuit 14 via the next D flip-flop circuit. For example, pixel data D
Is a D flip-flop circuit 17, a D flip-flop circuit
16, the D flip-flop circuit 15 and the D flip-flop circuit 14 sequentially pass through the D flip-flop circuit with a delay of three dot clock signals from the pixel data A.
It will be output from the 14 output terminals Q. As described above, the five data are subjected to parallel / serial conversion.

The operation will be described with reference to the timing chart of FIG. Here, up to time t _0, the external clock signal LD
The dot clock signal DCK is assumed to be synchronized, and the sixth D flip-flop circuit 12 outputs an internal clock signal LDL synchronized with the dot clock signal DCK in the same cycle as the external clock signal LD. Shall be

When set to "1" at time t ₁ to the external clock signal LD to be "1" at time t ₀ is delayed approximately one clock period from time t _0, in this state during the one cycle of the external clock signal LD In this case, the display processing is performed six times, and the screen is disturbed. However, this time, the third output signal S ₃ is "0", the timing shift detection signal CR is time t _2, the becomes "0". Therefore, the 6D flip-flop circuit 12 is forced to a possible clearing is applied, so that the rise of the internal clock signal is delayed until time t _3. Therefore, the following 5
The internal clock signal LDL rises after the pixel data has reliably reached the parallel / serial conversion circuit, and it is possible to avoid shifting to the display processing before data is input. Therefore, the disturbance of the screen due to the timing deviation is minimized.

〔The invention's effect〕

Since the present invention is configured as described above, an internal clock signal synchronized with the first clock signal in the same cycle as the external clock signal is generated in the information processing device by inputting an external clock signal according to the purpose. Then, since the parallel / serial conversion of the data is performed based on this, even if the external clock signal is shifted, the influence of the timing shift can be minimized by correcting the internal clock signal. Since the data conversion error due to the timing shift can be reduced and the influence on the serial data processing can be reduced, for example, in the case of the drawing processing, the display can be performed with the disturbance of the image minimized. To play.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a parallel / serial conversion circuit, FIG. 3 is a timing chart of a synchronous circuit, FIG. FIG. 6 is an explanatory diagram of a display operation of pixel data, FIG. 6 is an explanatory diagram of drawing and capture timing, FIG. 7 is an explanatory diagram of a timing shift between a dot clock signal and an external clock signal, and FIG. It is a more specific explanatory drawing. DESCRIPTION OF SYMBOLS 1 ... Synchronization circuit 2 ... Timing deviation detection circuit 3 ... Internal synchronization circuit 4 ... 1st D flip-flop circuit 5 ... 2D flip-flop circuit 6 ... 1st NAND circuit 7 ... 2nd NAND circuit 8 ... Buffer Circuit 9 3D flip-flop circuit 10 4th D flip-flop circuit 11 5th D flip-flop circuit 12 6th D flip-flop circuit 13 parallel / serial conversion circuit 14-18 D flip-flop circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 5/12 G06F 5/00 G09G 5/00 H04N 1/21

Claims (1)

(57) [Claims] A plurality of pixel data (A to E) are fetched in parallel based on an external clock signal (LD), the plurality of pixel data are converted to serial data, and the serial data is converted to the external clock signal (LD). ) Is a parallel / parallel signal that is output in synchronization with the asynchronous first clock signal (DCK).
In the image processing apparatus provided with the serial conversion means (13), the external clock signal (LD) is input, has the same cycle as the external clock signal (LD), and is synchronized with the first clock signal (DCK). Generating the second clock signal (LDL), outputting the second clock signal (LDL) to the parallel / serial conversion means (13) as a timing for taking in the plurality of pixel data (A to E). ,
When the rise of the external clock signal (LD) and the rise of the first clock signal (DCK) approach within a predetermined time, the synchronization circuit (1) delays the rise of the second clock signal (LDL). After delaying the rise of the second clock signal (LDL), only the plurality of pixel data (A to E) captured by the parallel / serial conversion means (13) is converted to the first data.
An image processing apparatus for sequentially outputting serially in synchronization with a clock signal (DCK).