JPS6118988A - Display synchronization circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is suitable for use in display device control of an apparatus including data processing control. In particular, two large-scale integrated circuits for display control
The present invention relates to a display synchronization circuit for a display control circuit using two or more display control circuits.

[Conventional technology]

FIG. 2 is a block diagram of a conventional display synchronization circuit.

Conventionally, display control large-scale integrated circuits (hereinafter referred to as LSIs) have been used.

), as shown in Figure 3, the synchronization between LSIII and LSI21 is performed by the master LSI.
LSI that uses the vertical synchronization signal of II as a slave
The delay circuit 24 of the display control circuit 20 adjusts the display positions of the display control circuit 10 and the display control circuit 20.

FIG. 4 is a time chart of a vertical synchronization signal of a large-scale integrated circuit in a conventional display control synchronization circuit.
This shows a state where II and LSI 21 are synchronized. In FIG. 4, b is a blanking signal of the LSIII, C is a clock signal, d is a blanking signal of the LSI 21, and e is a vertical synchronization signal.

[Problem that the invention seeks to solve]

However, this delay circuit has the disadvantage that the circuit scale becomes large because it delays in units of dots, and in the case of a dot memory such as a color display, it requires a circuit twice as many as the number of surfaces.

The present invention solves these drawbacks, and allows the synchronization positions of a plurality of display control LSIs to be freely set.
Another object of the present invention is to provide a display synchronization circuit with a small circuit scale.

[Means for solving problems]

The present invention includes a master display control large-scale integrated circuit that inputs commands and data from the outside to a data terminal and outputs a display control signal, and M types (M is 1 or more) different from the above commands and data from the outside. inputs commands and data (an integer of M) to each data terminal, inputs information on the output signal from the vertical synchronizing signal terminal of the large-scale integrated circuit to the vertical synchronizing signal terminal, and outputs each display control signal. In a display synchronization circuit equipped with slave display control large-scale integrated circuits, the output signal from the vertical synchronization signal terminal of one master display control large-scale integrated circuit is input, and this output signal is temporarily The present invention is characterized in that it includes a shift register for storing and applying the data to the vertical synchronizing signal terminals of the M slave display control large-scale integrated circuits.

[For production]

The present invention inputs an output signal from a vertical synchronization signal terminal of one master display control large-scale integrated circuit that inputs external commands and data to a data terminal and outputs a display control signal, and inputs an output signal from a vertical synchronization signal terminal to a shift register. Mf different from the above from the outside
The above shift is performed to the vertical synchronization signal terminals of M slave display control large-scale integrated circuits that manually input commands and data of the ffi class (M is an integer greater than or equal to 1) to their respective data terminals and output respective display control signals. By providing signals delayed by a predetermined time from the above output signals from the register, it is possible to synchronize (M+1) types of display positions.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a display synchronization circuit according to an embodiment of the present invention. Commands and data from outside the figure are connected to the data bus DB of the LSIII in the display control circuit 10 via the bus β. A character address signal from the address data bus AD of the LSIII is connected to the launch circuit 12, and the output of the launch circuit 12 is connected to the code memo 3 via the bus. In addition, the LSIII address data bus AD
The character data is sent to the code memory 13 via the bus.
connected to. From code memo January 3, data is connected to the character generator 14 via the bus. Furthermore, commands and data are input from outside the figure to the data bus DB of the LSI 21 in the display control circuit 20 via the bus β. A dot address signal is connected to the launch circuit 22 from the address data bus AD of the LSI 21 via the bus.

The output of the launch circuit 22 is sent to the memory 23 via the bus.
connected to. Further, dot data is transferred from the address data bus AD of the LSI 21 to the dot memory 23 via the bus.
connected to.

Output of character generator 14 and dot memory 23
The outputs of the OR circuit 30 are connected to the inputs of the OR circuit 30, and the output of the OR circuit 30 is connected to a display device (not shown). L.S.
The output of the blanking output BLANK of III is connected to a display device not shown. The output clock signal of the clock generation circuit 40 is connected to the clock inputs of the LSIII and the LSI 21.

Here, the feature of the present invention is the synchronization position adjustment portion surrounded by a dashed line. The clock signal is also connected to the clock input of shift register 50. LSII
The output signal from the vertical synchronizing signal terminal VSYN of I is connected to the input of the shift register 50, and the output of the shift register 50 is connected to the vertical synchronizing signal terminal VSYN of the LSI 21. The LSIs for display control used in this example are μPD7220.

The operation of the display synchronization circuit having such a configuration will be explained.

Commands and data are given to LSIII and LSI 21 via bus l, and display data is written into code memory and tont memory. The code read from the code memory is converted into a dot pattern by the character generator 14, and the data is ORed with the data read from the tone memory by the OR circuit 30 and transferred to the display device. L.S.
I21 is initial reset at the fall of the input signal of the vertical synchronizing signal terminal VSYN, and is synchronized with S I11. The synchronization time relationship between LS11 and LSI 21 can be freely set by changing the number of output stages of shift register 50.

In order to match the positions of the display control circuit 10 and the display control circuit 20 on the display screen, in the conventional circuit, a delay circuit 24 is inserted after the dot memory 23 to match the time between A+B+ and the time between A2B2. However, in this embodiment, the vertical synchronization signal, which is a synchronization signal, is transferred to the shift register 50.
The position is adjusted with a delay. With this configuration, the number of circuits can be significantly reduced. For example, A+B+
If there is a time difference of one code, that is, one character, between
3 must be delayed by 16 dots. That is, 16 flip-flops were required, but in this embodiment, if the vertical synchronization signal output from the LSIII is delayed by 2 clocks, the output of the memory 23 will be delayed by 16 dots. That is, 16 flip-flops are reduced to two. If the number of memory surfaces increases, such as in the case of color control, the difference in circuit scale will further increase. In this embodiment, LSIII and LSI2 are arranged so that one code is read out in two clocks.
1 is set. FIG. 4 is a time chart of the vertical synchronization signal of the large-scale integrated circuit in the display synchronization circuit of the present invention, where a is the vertical synchronization signal of LSIII, and b is r-sr.
ll blanking signal, C clock signal, d LS
A blanking signal of I21, e a vertical synchronizing signal of LSI 21, and f the number of clocks delayed by shift register 50.

The case where there are two display control LSIs has been explained above, but
Even when there are three or more display field 411 LSIs, the synchronization position can be freely set as described above by providing a shift register corresponding to the slave display control LSI.

〔Effect of the invention〕

As explained above, in the present invention, a shift register is inserted between the vertical synchronization signal terminals of one master display control LSI and M slave display control LSIs, and the master display control LSI
By delaying the output signals from the vertical synchronizing signal terminals of the SI by a predetermined time and applying them to the vertical synchronizing signal terminals of the M display control LSIs, it is possible to synchronize (M+1) display positions. It has an excellent effect of reducing the scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display synchronization circuit according to a first embodiment of the present invention. FIG. 2 is a time chart of signals of a large-scale integrated circuit in the display synchronization circuit of the present invention. FIG. 3 is a block diagram of a conventional display synchronization circuit. FIG. 4 is a time chart of signals of a large-scale integrated circuit in a conventional display synchronization circuit. 10.20...Display control circuit, 11.21...Large scale integrated circuit, 12.22...Latch circuit, 13...
Code memory, 14...Character generator, 2
3... Dot memory, β... Nomas. Patent applicant: NEC Corporation.

Claims (1)

[Claims] (1) One master display control large-scale integrated circuit that inputs commands and data from the outside to the data terminal and outputs display control signals, and M types of external commands and data different from the above (
M is an integer of 1 or more) commands and data are input to each data terminal, information on the output signal from the vertical synchronization signal terminal of the large-scale integrated circuit is input to the vertical synchronization signal terminal, and each display control signal is input. In a display synchronization circuit equipped with M slave display control large-scale integrated circuits that output 1. A display synchronization circuit comprising a shift register which temporarily stores and supplies the data to the vertical synchronization signal terminals of the M slave display control large-scale integrated circuits.