JP2000278252A - Device and method for synchronizing asynchronous signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for synchronizing asynchronous signal where the existing specification definition technology for an asynchronous signal can be followed, it is not required to increase specification definitions for the clock and synchronization can be warranted with a minimum clock pulse width, and to provide an asynchronous signal synchronization method. SOLUTION: The device is provided with a single phase synchronization circuit 100 that has a 1st synchronization latch circuit 20 and a 2nd synchronization latch circuit 30 which are connected in cascade. The device uses the 1st synchronization latch circuit 20 and the 2nd synchronization latch circuit 30 to apply synchronization processing to received digital asynchronous data strobe signal/WR so as to generate a synchronized data strobe signal 40a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous signal synchronizing technique for synchronizing a digitally transmitted signal with a clock on a receiving side, and more particularly to a technique for defining specifications between current asynchronous signals. The present invention relates to an asynchronous signal synchronizer and an asynchronous signal synchronizing method that guarantee a synchronous operation with a minimum clock pulse width without having to increase clock specifications.

[0002]

2. Description of the Related Art In recent years, the number of digital circuits that are logically synthesized from a higher-level description has increased, and the number of synchronous circuits has increased. To describe it, the circuit must be a synchronous circuit. In order to meet such a need, an asynchronous signal synchronizer for synchronizing a digitally transmitted signal with a clock on a receiving side has been actively developed. Such conventional techniques include:
For example, there is one described in JP-A-10-135938. That is, in the related art, a first flip-flop that takes in an input data strobe signal at a rising edge of a clock signal, a second flip-flop that takes in an output of the first flip-flop at a rising edge of a clock signal, and the first flip-flop. A gate that outputs the logical product of the output of the flip-flop and the inverted output of the second flip-flop, and a third flip-flop that takes in the input data signal when the output of the gate is true and the clock signal rises. An n-bit shift register (n is an integer) for taking in an external input signal at the rising edge of the external clock signal; a bit number detecting means for detecting that n-1 data has been input into the shift register; Fourth flip-flop which takes in the output of the detecting means at the rising edge of the external clock signal Comprising a flop, the output of the shift register as input data signals, an asynchronous signal synchronization circuit for receiving the data strobe signal output of the fourth flip-flop. Thus, a first flip-flop that captures the data strobe signal at the rising edge of the clock signal and a second flip-flop that captures the output of the first flip-flop at the rising edge of the clock signal,
A gate for outputting a logical product of the output of the first flip-flop and the inverted output of the second flip-flop; and a third flip-flop for taking in the input data signal when the output of the gate is true and the clock signal rises. Thus, it is disclosed that logic synthesis can be performed at the time of design, so that design cost can be reduced, and since a test pattern does not include an uncertain time element, the quality of a product can be reliably determined.

[0003]

However, the prior art has a problem in the timing of the cut of the circuit. That is, in the prior art, if the asynchronous input is simply synchronized, two stages of flip-flops are used and the asynchronous signal is generated by the synchronous clock. Therefore, the definition of the pulse width of the asynchronous input signal is defined in units of the cycle of the synchronous clock. Therefore, there is a problem that it is necessary to input a longer pulse as the synchronous clock becomes slower.

The present invention has been made in view of such a problem, and an object of the present invention is to be able to follow the specification definition technique between the current asynchronous signals, to eliminate the need to increase the specification for the clock, and to minimize the specification. An object of the present invention is to provide an asynchronous signal synchronizer and an asynchronous signal synchronizer method that guarantee a synchronous operation with a clock pulse width.

[0005]

SUMMARY OF THE INVENTION The gist of the first aspect of the present invention is to follow the technique for defining the specifications between the currently used asynchronous signals, there is no need to increase the specifications for the clock, and the minimum clock pulse width is not required. An asynchronous signal synchronizing device for guaranteeing a synchronous operation, comprising a circuit in which a first synchronizing latch circuit and a second synchronizing latch circuit, which receive a synchronous clock as a clock input, are cascaded in two stages, and digitally transmitted. Having a one-phase synchronization circuit configured to synchronize the asynchronous data strobe signal using the first synchronization latch circuit and the second synchronization latch circuit to generate a synchronous data strobe signal. An asynchronous signal synchronizer characterized by the following. Claim 2 of the present invention
The gist of the invention is that the one-phase synchronization circuit generates and outputs an asynchronous signal detection flag signal triggered by a rise of the asynchronous data strobe signal, and outputs the asynchronous signal detection flag signal to the first synchronization latch. 2. The asynchronous signal synchronizer according to claim 1, further comprising an asynchronous signal detection circuit that outputs the signal as a signal for circuit synchronization. According to another aspect of the present invention, in the one-phase synchronization circuit, when the asynchronous signal detection flag signal is input to the first synchronization latch circuit, contention occurs with the synchronization clock. 2. In this case, the second synchronization latch circuit is configured to perform synchronization processing with the synchronization clock again to generate and output a second synchronization data strobe signal.
Alternatively, the present invention resides in the asynchronous signal synchronizer according to 2. The gist of claim 4 of the present invention is that the one-phase synchronization circuit has a circuit configuration in which the second synchronization data strobe signal of the second synchronization latch circuit is fed back to the asynchronous signal detection circuit. 4. The asynchronous signal synchronizer according to claim 3, wherein: Claim 5 of the present invention
The gist described in is an asynchronous signal synchronization method that can follow the specification definition technique between the current asynchronous signals, does not need to increase the specification of the clock, and guarantees the synchronous operation with the minimum clock pulse width. A first synchronizing latch circuit and a second synchronizing latch circuit having a clock input as a clock input, wherein the first and second synchronizing latch circuits are cascaded in two stages, and the digitally transmitted asynchronous data strobe signal is transmitted to the first synchronizing latch circuit. And a one-phase synchronization processing step configured to perform synchronization processing using a second synchronization latch circuit to generate a synchronization data strobe signal. The gist of claim 6 of the present invention is that the one-phase synchronization processing step comprises:
Asynchronous signal detection that generates and outputs an asynchronous signal detection flag signal with a rising edge of the asynchronous data strobe signal as a trigger, and outputs the asynchronous signal detection flag signal as a signal for synchronization of the first synchronization latch circuit. 6. The method for synchronizing an asynchronous signal according to claim 5, comprising a step. Claim 7 of the present invention
The gist of the invention is that, in the one-phase synchronization processing step, when a conflict occurs with the synchronization clock when the asynchronous signal detection flag signal is input to the first synchronization latch circuit, 7. The asynchronous signal synchronization according to claim 5, further comprising the step of: generating a second synchronous data strobe signal by outputting a second synchronous data strobe signal by the synchronization latch circuit performing synchronization processing with the synchronous clock again. Be in the way. The gist of claim 8 of the present invention is that the one-phase synchronization processing step includes the step of:
The method according to claim 7, further comprising a step of feeding back a synchronous data strobe signal to the asynchronous signal detecting step.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram for explaining a one-phase synchronous circuit 100 provided in an asynchronous signal synchronizer according to one embodiment of the present invention. Referring to FIG. 1, a one-phase synchronous circuit 100 according to the present embodiment includes an asynchronous signal detection circuit (first D-type flip-flop) 1
0, a first synchronization latch circuit (second D-type flip-flop) 20, a second synchronization latch circuit (third D-type flip-flop) 30, and OR logic elements 40 and 50. In the asynchronous signal detection circuit (first D-type flip-flop) 10, the D terminal is pulled up to a constant potential (for example, a power supply potential), and the asynchronous data strobe signal / WR (/ means negative logic) at the C terminal. ), The reset signal 50a of the OR logic element 50 is input to the R terminal, and the asynchronous signal detection flag signal 10a is supplied to the next-stage first synchronization latch circuit (second D-type flip-flop) 20 via the Q terminal. It is configured to be input to the D terminal. The first synchronization latch circuit (second D-type flip-flop) 20
The asynchronous signal detection flag signal 10a is input to the D terminal, the synchronous clock CLK is input to the C terminal, the reset signal RST is input to the R terminal, and the first synchronous data strobe signal 20a is input via the Q terminal to the second-stage second synchronization latch. The circuit (third D-type flip-flop) 30 is configured to be input to the D terminal. The second synchronization latch circuit (third D-type flip-flop) 30 receives the first synchronization data strobe signal 20a at the D terminal, the synchronization clock CLK at the C terminal, and the reset signal RST at the R terminal. Synchronous data
The strobe signal 30a is configured to be input to the input terminals of the OR logic elements 40 and 50 at the next stage via the Q terminal. The OR logic element 40 includes a first synchronous data strobe signal 20a and a second synchronous data strobe signal 3
It is configured to execute a logical sum operation with 0a to generate a synchronous data strobe signal 40a and output it to the asynchronous data bus interface 200. The OR logic element 50 outputs a reset signal 50a generated by executing a logical OR operation of the reset signal RST and the second synchronous data strobe signal 30a to an R terminal of the asynchronous signal detection circuit (first D-type flip-flop) 10. Is configured to be output.

FIG. 2 is a circuit diagram for explaining an asynchronous data bus interface 200 provided in the asynchronous signal synchronizer according to one embodiment of the present invention. Referring to FIG. 2, the asynchronous data bus interface 200 according to the present embodiment includes a data bus buffer (fourth D-type flip-flop) 60, a selector 70, and a write destination register (fifth D-type flip-flop) 80. ing. The data bus buffer (fourth D-type flip-flop) 60 is a D-type flip-flop, and is a data signal DI (7:
0), the asynchronous data strobe signal / WR,
The reset signal RST is input to the R terminal, and the output signal 60
a is input to the input terminal 1 of the next-stage selector 70 via the Q terminal.

In the selector 70, a synchronous data strobe signal 80a generated and output by a write destination register (fifth D-type flip-flop) 80 is input to an input terminal 0, and an output signal 60a is input to an input terminal 1, respectively. A signal corresponding to the logical value of data strobe signal 40a is output signal 7
It is configured to be input to the D terminal of the write destination register (fifth D-type flip-flop) 80 as 0a.

In a write destination register (fifth D-type flip-flop) 80, an output signal 70a is input to a D terminal, a synchronous clock CLK is input to a C terminal, and a reset signal RST is input to an R terminal. Signal 8
0a is an external circuit (not shown) and the input terminal 0 of the selector 70.
It is configured to be inputted to.

Next, the asynchronous data bus interface 20
The operation 0 (asynchronous signal synchronization method) will be described. FIG. 3 is a timing chart for explaining the operation of the asynchronous signal synchronizer according to one embodiment of the present invention. The data bus buffer (fourth D-type flip-flop) 60 shown in FIG. 2 performs the same asynchronous reception as the asynchronous circuit. The data signal DI (7: 0) received at the asynchronous reception timing of the asynchronous circuit is synchronized with the asynchronous data strobe signal / WR at the timing shown in FIG. 3 for the data bus buffer (fourth D-type flip-flop). It is taken into 60. The synchronization of the asynchronous data strobe signal / WR used in the one-phase synchronous circuit 100 of FIG. 1 is performed by synchronizing the asynchronous data strobe signal / WR, which is the data fetch timing of the data bus buffer (fourth D-type flip-flop) 60. The asynchronous signal detection flag signal 10a generated and output by the asynchronous signal detection circuit (first D-type flip-flop) 10 triggered by the rising edge is connected to the subsequent stage of the asynchronous signal detection circuit (first D-type flip-flop) 10. Two stages of the first synchronizing latch circuit (the second D
And a second synchronizing latch circuit (third D-type flip-flop) 30. Asynchronous signal detection circuit (first D
Type flip-flop) 10 generates and outputs an asynchronous signal detection flag signal 10a to a first synchronization latch circuit (second
In some cases, a conflict may occur with the synchronous clock CLK when the data is input to the D-type flip-flop 20). In such a case, the second synchronization latch circuit (third D-type flip-flop) 30 is used. Second synchronization data strobe signal 30 that has been synchronized with synchronization clock CLK again
There is no problem because a is generated and output. Synchronous data strobe signal 4 generated and output by one-phase synchronous circuit 100 in FIG.
0a is taken into the selector 70 at the timing shown in FIG. The output signal 70a from the selector 70 is shown in FIG.
At the timing of the synchronization signal CLOCK shown in FIG. A write destination register (fifth D-type flip-flop) 80 is a write destination register, which fetches the output signal 70a from the selector 70 at the timing of the synchronization signal CLOCK shown in FIG.
Output as strobe signal 80a. Using the synchronous data strobe signal 40a, the selector 70 is controlled at the timing shown in FIG.
Output signal 60 synchronized by the flip-flop 60)
is transmitted to the write destination register (fifth D-type flip-flop) 80. The output signal 60a is a synchronous clock C
The data is written to the write destination register (fifth D-type flip-flop) 80 at the timing of LK. In the present embodiment, the asynchronous data strobe signal / WR does not depend on the synchronous clock CLK, but the write cycle (from the active end of the asynchronous data strobe signal / WR to the active end of the next asynchronous data strobe signal / WR). Time) is based on the cycle of the synchronous clock CLK.

As a prior art similar to the present invention,
For example, JP-A-58-79329 and JP-A-4-1
No. 37815, JP-A-10-135938,
There is one described in JP-A-10-149335.
The prior art described in Japanese Patent Application Laid-Open No. 58-79329 uses an anti-phase synchronous clock, an SR latch, and a differentiating circuit, and is fundamentally different from the idea of the one-phase synchronous circuit 100 which is the background of the present invention. Is different. In the prior art described in Japanese Patent Application Laid-Open No. 4-137815, the hazard of a signal emitted from an asynchronous circuit is eliminated by synchronizing with a D-type flip-flop at the subsequent stage. In order to apply to the one-phase synchronous circuit 100 without changing the definition of AC specifications between asynchronous signals set at the macro cutoff, the asynchronous signals are directly input to each other by the first stage D-type flip-flop. And
This is taken in at the timing of a synchronized asynchronous data strobe signal, and the circuit configuration of the data taking part is different from that of the prior art described in JP-A-4-137815. In addition, the circuit configuration using the flip-flop also has a configuration in which the first-stage asynchronous signal detection circuit (first D-type flip-flop) 10 is connected to the second-stage second synchronization latch circuit (third D-type flip-flop) 30. 2 synchronous data strobe signal 30a (ie, reset signal 5
The circuit configuration for feeding back 0a) is different from the present invention. Further, the circuit configuration described in the prior art described in Japanese Patent Application Laid-Open No. H10-135938 uses an anti-phase synchronous clock and does not have the configuration of the one-phase synchronous circuit 100.
The present invention does not have a circuit configuration capable of realizing the purpose of "applying the specification definition between the current asynchronous signals set at the macro cutoff to the one-phase synchronous circuit 100". The PCI of the prior art described in JP-A-10-149335 is originally a synchronous circuit,
The AC specifications are only those for the synchronous clock CLK. Therefore, in the prior art described in Japanese Patent Application Laid-Open No. H10-149335, "the specification definition between the currently used asynchronous signals set at the macro cutoff is applied to the one-phase synchronous circuit 100". The purpose of "doing".

As described above, according to the present embodiment, the asynchronous data strobe signal / WR is detected by the first-stage asynchronous signal detection circuit (first D-type flip-flop) 10 and the asynchronous signal detection flag signal is detected. 10a, and generates and outputs a second synchronization data strobe signal 30a that has been synchronized with the synchronization clock CLK again using the second synchronization latch circuit (third D-type flip-flop) 30. Output, the asynchronous signal detection flag signal 10a
And the synchronization clock CLK can be prevented,
Further, the synchronization condition can be made independent of the synchronization clock CLK. As a result, even when a low-speed operation is required, the synchronization processing can be performed in the same manner as before.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately changed within the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment,
The number, position, shape, and the like suitable for carrying out the present invention can be obtained. In each drawing, the same components are denoted by the same reference numerals.

[0014]

Since the present invention is configured as described above, the asynchronous data strobe signal is detected by the first-stage asynchronous signal detection circuit (first D-type flip-flop) to generate the asynchronous signal detection flag signal. Output and use the second synchronization latch circuit (third D-type flip-flop) to generate and output a signal that has been synchronized with the synchronous clock again, so that the asynchronous signal detection flag signal and the synchronous clock And the synchronization condition can be made independent of the synchronization clock. As a result, even when a low-speed operation is required, the synchronization processing can be performed in the same manner as before.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for explaining a one-phase synchronous circuit provided in an asynchronous signal synchronizer according to an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an asynchronous data bus interface provided in the asynchronous signal synchronizer according to one embodiment of the present invention;

FIG. 3 is a timing chart for explaining the operation of the asynchronous signal synchronizer according to one embodiment of the present invention;

[Explanation of symbols]

10: Asynchronous signal detection circuit (first D-type flip-flop) 10a: Asynchronous signal detection flag signal 20: first synchronization latch circuit (second D-type flip-flop) 20a: first synchronous data strobe signal 30 ... second synchronization latch circuit (third D-type flip-flop) 30a ... second synchronization data strobe signal 40, 50 ... OR logic element 40a ... synchronization data strobe signal 50a ... reset signal 60 ... data bus buffer ( A fourth D-type flip-flop) 60a output signal 70 selector 70a output signal 80 write destination register (fifth D-type flip-flop) 80a synchronous data strobe signal 100 single-phase synchronous circuit 200 asynchronous data Bus interface CLK: Synchronous clock DI (7: 0): Data signal RST ... Reset signal / WR ... Asynchronous data strobe signal (/ means negative logic)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masahiro Wakushima 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term within NEC Icy Microcomputer Systems Co., Ltd. 5B077 FF01 GG13 MM01 MM02 5K047 AA01 GG07 GG24 MM27 MM28 MM53

Claims (8)

[Claims] 1. An asynchronous signal synchronizer which can follow a specification definition technique between current asynchronous signals, does not need to increase the specification of a clock, and guarantees a synchronous operation with a minimum clock pulse width. And a circuit in which a first synchronizing latch circuit and a second synchronizing latch circuit, each of which has a clock input, are connected in cascade, and the digitally transmitted asynchronous data strobe signal is transmitted to the first synchronizing latch circuit. Second
An asynchronous signal synchronizer comprising a one-phase synchronous circuit configured to generate a synchronous data strobe signal by performing a synchronization process using a latch circuit for synchronization. 2. The one-phase synchronization circuit generates and outputs an asynchronous signal detection flag signal triggered by a rise of the asynchronous data strobe signal, and outputs the asynchronous signal detection flag signal to the first synchronization latch circuit. 2. The asynchronous signal synchronizer according to claim 1, further comprising: an asynchronous signal detection circuit that outputs the signal as a signal for synchronization. 3. The one-phase synchronization circuit, wherein when the asynchronous signal detection flag signal is input to the first synchronization latch circuit and a conflict occurs with the synchronization clock, the second synchronization is performed. 3. The asynchronous signal synchronization according to claim 1, wherein the latch circuit is configured to perform a synchronization process with the synchronization clock again to generate and output a second synchronization data strobe signal. 4. Device. 4. The circuit according to claim 1, wherein the one-phase synchronization circuit has a circuit configuration in which the second synchronization data strobe signal of the second synchronization latch circuit is fed back to the asynchronous signal detection circuit. 4. The asynchronous signal synchronizer according to 3. 5. An asynchronous signal synchronizing method which can follow a specification definition technique between current asynchronous signals, does not need to increase the specification of a clock, and guarantees a synchronous operation with a minimum clock pulse width. And a circuit in which a first synchronizing latch circuit and a second synchronizing latch circuit, each of which has a clock input, are connected in cascade, and the digitally transmitted asynchronous data strobe signal is transmitted to the first synchronizing latch circuit. Second
An asynchronous signal synchronization method comprising a one-phase synchronization processing step configured to perform synchronization processing using a synchronization latch circuit to generate a synchronous data strobe signal. 6. The one-phase synchronization processing step includes: generating and outputting an asynchronous signal detection flag signal with a rising edge of the asynchronous data strobe signal as a trigger; and outputting the asynchronous signal detection flag signal to the first synchronization latch. 6. The asynchronous signal synchronization method according to claim 5, further comprising an asynchronous signal detection step of outputting the signal as a signal for circuit synchronization. 7. The one-phase synchronization processing step includes: when a conflict occurs with the synchronization clock when the asynchronous signal detection flag signal is input to the first synchronization latch circuit, the second synchronization is performed. 7. The method according to claim 5, further comprising the step of: performing a synchronization process with the synchronization clock again to generate and output a second synchronization data strobe signal. . 8. The one-phase synchronization processing step includes a step of feeding back the second synchronization data strobe signal of the second synchronization latch circuit to the asynchronous signal detection step. 3. The method for synchronizing asynchronous signals according to item 1.