JPH0282812A - Clock switching system - Google Patents

Abstract

PURPOSE:To guarantee the width of a clock pulse at switching and to prevent a pulse with a shorter width from being outputted by stopping and outputting a clock in a timing synchronously with its own clock. CONSTITUTION:A system is employed in order to switch a clock CLKA 11 into a clock CLKB 12 in such a way that the CLKA 11 is masked at the first trailing point of time of the clock CLKA 11 after a change in a clock switching signal 10, for example, and its output is stopped and then the CLKB 12 is outputted in a timing synchronously with the clock CLKB 12. Thus, the pulse width is not shortened in the stop of the clock CLKA 11 and in the output stage of the clock CLKB 12. The clock CLKA 11 is outputted in the timing synchronously with the clock CLKA 11 after the clock CLKB 12 is stopped in the timing syuchronously with the clock CLKB 12 entirely the same as the case with the clock switching from the clock CLKB 12 into the clock CLKA 11.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a clock switching method that guarantees a clock pulse width at the time of clock switching by stopping and outputting the two clocks to be switched at a timing synchronized with the self-clock. The purpose of this is to guarantee the clock pulse width at the time of switching and prevent malfunction of the circuit by performing the stop F and output at a timing synchronized with the self clock. In the clock switching circuit, the first signal masking means masks the first clock in synchronization with the first clock, and the second signal masking means synchronizes with the second clock and outputs the second clock. and second signal masking means for masking the first clock, and when switching from the first clock to the second clock, the first clock is masked by the first signal masking means, and then the second clock is masked by the first signal masking means. The second clock is unmasked by the signal masking means to output the second clock, and when switching from the second clock to the first clock, the second clock is unmasked by the second signal masking means. After masking the second clock, the first clock is unmasked by the first signal masking means and the first clock is output.

[Industrial application field]

The present invention relates to a method for switching clock pulses in various electronic circuits, etc., and more specifically, a clock that guarantees the clock pulse width when switching clocks by stopping two clocks to be switched and outputting them at a timing synchronized with the self-clock. Switching Method [Prior Art] Various clocks with different periods and pulse widths are used as clock pulses for signal synchronization in electronic circuits and computer systems, and for the time axis of transmission systems, depending on where they are used in the circuit or system. For example, when a terminal uses a bus system clock and a line output clock that are asynchronous to each other, it is necessary to switch the clocks at an appropriate location inside the terminal.

A conventional example of a switching method that performs lock switching like this is shown in the fourth example.
As shown in the figure. In the same figure, 1 indicates two clocks (CLK)
This is a selector for switching and outputting A and B. For example, when CLK switching signal 2 is "1", CLKA3 is output from selector 1 as output (CLKOUT) 4,
When the CLK switching signal is "0", CLKB5 is output from the selector 1.

[Problem to be solved by the invention]

A time chart of clock switching in the conventional example of the clock switching method shown in FIG. 4 is shown in FIG. In the same figure, C
LK9] In the section where the switching signal 2 is "1", CLKA3 is set to CLKO, and in the section where the switching signal 2 is "0°", CLKB5 is set to CLKO.
Output as UT4. In the same figure (a), CL
The K switching signal 2 changes from “1” to °0° at CLKA3.
This is the point after p when CLKB changes from 0° to 1, and therefore, a pulse with a very short width indicated by ■ is output to CLKOUT4.
Immediately after 5 changes from "0" to "1", CLK switching signal 2
changes from 0 to 1, and a short pulse shown by black is output to CLKOUT4.

If a signal including pulses having a short width as described above is used as a clock, it may cause malfunction of the digital circuit. Therefore, there is a problem in that a circuit for removing such short width pulses is required.

The present invention achieves this by stopping and outputting the two clocks to be switched at a timing synchronized with the self-clock.
Guarantees clock pulse width during switching to prevent circuit malfunction1
The purpose is to read.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. In the figure, switching between the first clock and the second clock is controlled by a clock switching signal.

The first signal masking means 6 masks the first clock at a timing synchronized with the first clock, for example, in synchronization with the falling edge of the first clock pulse, and the first signal masking means 6 masks the first clock at a timing synchronized with the first clock, for example, in synchronization with the falling edge of the first clock pulse. The first clock is masked after the falling edge of the first first clock pulse in the first clock pulse.

The second signal masking means 7 masks the second clock at a timing synchronized with the second clock, for example, in synchronization with the falling edge of the second clock pulse, and the second signal masking means 7 masks the second clock at a timing synchronized with the second clock, for example, in synchronization with the falling edge of the second clock pulse. The second clock is masked after the falling edge of the first second clock pulse in the second clock pulse.

[For production]

In FIG. 1, for example, it is assumed that the first clock is output when the clock switching signal is "1°" and the second clock is output when the clock switching signal is "0°." When switching from the first clock to the second clock, the clock switching signal is changed from °1' to "0". Immediately after this change, at the falling edge of the first clock pulse, the first signal masking means 6 The first
The first clock is masked, and the output of the first clock is stopped. Before this point, since the first clock is being output, the second clock is naturally masked by the second signal masking means 7, but at the falling edge of the second clock pulse immediately after this point, the second clock is output. The second signal masking means 7 is unmasked and output of the second clock is started.

On the other hand, when switching from the second clock to the first clock, the clock switching signal is changed from 0' to 1'. Immediately after this change, at the falling edge of the second clock pulse, the second clock is masked by the second signal masking means 7, and its output is stopped. Thereafter, the masking of the first clock by the first signal masking means 6 is released at the falling edge of the first clock pulse, and output of the first clock is restarted.

As described above, in the present invention, in order to stop and output the clock at a timing synchronized with the self-clock,
The clock pulse width at the time of switching is guaranteed, and short pulses will not be output.

〔Example〕

An embodiment of the clock switching circuit according to the present invention is shown in FIG. The circuit shown in the figure is controlled by the clock switching signal 10.
It switches two clocks CL'KAII and CLKB12 and outputs them as CLKOUT20, and three D flip-flops (D-FF) 13, 14, 15.3
AND circuits 16, 17, and 18, and OR circuit 19
Consisted of.

In the present invention, when switching from CLKAII to CLKB12, first the timing synchronized with CLKAI 1, for example, the first CLK signal after the change of the clock switching signal 10.
At the falling edge of the KAI 1 pulse, CLKAII is masked and its output is stopped, and then CLKB 1
A method is used in which CLKB 12 is output at a timing synchronized with CLKB 2. As a result, the pulse width does not become short when CLKAII is stopped and CLKB12 is output.Even when switching the clock from CLKB12 to CLKAII, CLKB12 is stopped at a timing synchronized with CLKB12 in exactly the same way. C after being
CLKAll is output at a timing synchronized with LKAII.

The operation of the embodiment circuit shown in FIG. 2 will be explained with reference to the time chart shown in FIG. FIG. 3 is a time chart in which (al is delayed in phase of CLKB 12 with respect to CLKAll, (bl is in the opposite direction), and (C) is a time chart in which both phases match.

In FIG. 2, CLKAI input to the AND circuit 17
The stop output of I is controlled by the output of AND circuit 16, which is the other input to AND circuit 17, and the stop F output of CLKB12, which is input to AND circuit 18, is controlled by the other input to AND circuit 18. The output of the D-FF 14, which is the input, is controlled by the signal ◎.

First, switching from CLKA II to CLKB 12 will be explained. This is the operation in the first half of the time chart in FIG. For example, if the CLK switching signal 10 is "1" and CLKAII is 0, CLKB 12 is output, then in order to switch to CLKB12, the CLK switching signal 1o, that is, the (7) D input to the D-FF 13 is output. “
From 1゛ to 'o゛. Then, immediately after that, D-FF1
At the falling edge of the pulse of CLKAII, which is the clock input to CLKA II, the Q output of the D-FF 13 becomes "0".The Q output of the D-FF 13 is input to the AND circuit 16, so the output signal of the D-FF 13 becomes "0". becomes “0゛”, and the OR circuit 19 of CLKAll which is the other input to the AND circuit 17
Output via is stopped.

On the other hand, the Q output of the D-FF13 is also input to the D input of the D-FF14. CLKB, which is the clock input to D-FF 14 immediately after the Q output of D-FF 13 becomes °0°
At the falling edge of the pulse No. 12, the 100 output of the D-FF 14 and the signal O become "1°," and from this point on, the CLKB
12 is output via an AND circuit 18 and an OR circuit 19.

As described above, after the output of CLKAII is stopped in synchronization with the falling edge of the pulse of CLKAll, CLK, B12
Since output is started in synchronization with the falling edge of the pulse, both pulses CLKAI 1 and CLKB 12 are output with their pulse widths guaranteed.

Next, the switching from CLKB 12 to CLKAII, that is, the operation in the latter half of the time chart of FIG. 3 will be explained. When the CLK switching signal 10 changes from "O" to "1", the D-FF switches immediately after that at the falling edge of the CLKAI l pulse.
13's Q output becomes "1". This signal is D-FF 1
4, and is further transmitted to the Q output of the D-FF 14 at the falling edge of the CLKB12 pulse immediately thereafter. At this point, the output of the D-FF 14 becomes "0", and in synchronization with this, the output is stopped through the AND circuit 18 and the OR circuit 19 of the CLKB 12.

On the other hand, the Q output of D-FF14 is input to the D input of D-FF15, and at the falling edge of the CLKAI 1 pulse immediately after the Q output of D-FF14 becomes 11',
-The Q output of FF15 becomes "1", and this signal is input to the AND circuit 16.At this time, the Q output of D-FF13, which is the other input to the AND circuit 16, is already "1". , the output of the AND circuit 16, the signal Ill
From this point on, the output of CLKA II via the AND circuit 17 and the OR circuit 19 is restarted.

(a) to (C) in Figure 3 are CLKA II as described above.
This figure shows the difference due to the phase relationship between CLKB 12 and CLKB 12. To become, CLKB
A waveform with one pulse omitted when switching from CLKAII to CLKAII is obtained as CLKOUT20.

On the other hand, as shown in FIG. 3(b), CLKB l 2
(If the O phase is leading, the period from the fall of CLKA II to the fall of CLKB 12 is close to one cycle, so a waveform with one pulse missing when switching from CLKA II to CLKB 12 is obtained as CLKOUT 20.

Furthermore, as shown in Figure 3 (C), the phase of both clocks is lost,
In this case, for example, after the output of CLKAII is stopped by the falling edge of CLKAII, the output of CLKBl2 is started by the falling edge of CLKB 12 one pulse later, so that the switching from CLKAII to CLKB 12, and When switching from CLKBl 2 to CLKAII, the waveform with one pulse missing is CLKO.
Obtained as UT20.

In the above explanation, the case where the frequencies of CLKAII and CLKB 12 are equal has been explained, but even if the frequencies of both clocks are different, the pulse may vary depending on which clock pulse falls first after the change of the clock switching signal 10. The only difference is whether or not the output will be dropped, and there is no rigidity in the operation of the circuit shown in FIG. 2, and the present invention is also applicable to switching between two clocks having different frequencies.

〔Effect of the invention〕

As described above, according to the present invention, since the two clocks to be switched are stopped and output at timings synchronized with the self-clock, the clock pulse width at the time of switching is guaranteed, and malfunction of the circuit is prevented. This improves the reliability of the system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention; Fig. 2 is a diagram showing an embodiment of a clock switching circuit; Fig. 3 is a time chart in the embodiment; Fig. 4 is a diagram showing a conventional example of a clock switching system; FIG. 5 is a time chart in the conventional example. 13.14.15...D flip-flop, 16.1
7.18...AND circuit, ・OR circuit.

Claims (1)

[Claims] In a clock switching circuit that switches and outputs a first clock and a second clock using a clock switching signal, a first clock that masks the first clock in synchronization with the first clock; A signal masking means (6) and a second signal masking means (7) for masking the second clock in synchronization with the second clock are provided, At the time of switching, after the first clock is masked by the first signal masking means (6), the second clock is unmasked by the second signal masking means (7) and the second clock is output. However, when switching from the second clock to the first clock, after the second clock is masked by the second signal masking means (7), the first clock is masked by the first signal masking means (6). A clock switching method characterized in that the first clock is unmasked and the first clock is output.