JPH0336812A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To synchronize an input signal whose period is shorter than the clock period by providing a 2nd latch means receiving an input signal and an inverted clock signal and a means ORing outputs of 1st and 2nd latch means. CONSTITUTION:When an input signal D whose period is shorter than the period of a clock C is inputted to 1st DFF 12 and a 2nd DFF 13, an output X1 of the DFF 12 remains at an L level and an H level synchronously with the inverse of clock C is obtained at an output X2 of the DFF 13. Then the outputs X1, X2 are inputted to an OR gate 14 and an output X3 of the OR gate 14 is inputted to a 3rd DFF 15, then an H output X4 synchronously with the clock C is obtained from an output terminal Q of the DFF 15. Thus, even when the input signal whose period is shorter than the period of the clock, an output signal synchronously with the clock is obtained and the input signal with shorter period is synchronized without using the sophisticated clock synchronization.

Description

[Detailed Description of the Invention] [Summary] Regarding a synchronous circuit used in a circuit that operates in synchronization with a clock cycle, a synchronous circuit that can obtain an output signal synchronized with a clock even if the input signal is shorter than the clock cycle. an input signal including a signal shorter than a clock period is input to the data input terminal, a first holding means is input to the clock terminal, and the input signal is input to the data input terminal; and a second holding means to which an inverted clock signal of the clock signal is inputted to a clock terminal, an output of the first holding means and an output of the second holding means are inputted, and the logical sum of these outputs is calculated. The invention is characterized by having logical means for taking the following steps.

[Industrial application field]

The present invention relates to a synchronous circuit used in a circuit that operates in synchronization with a clock, and more particularly to a synchronous circuit that can generate an output in synchronization with a clock even when an input signal is shorter than the clock period.

When connecting synchronous logic circuits that use independent lock signals, or when applying an asynchronous input signal to a synchronous logic circuit, the change time of the input signal is determined by the rise (rise) of the clock signal of the circuit to which it is applied. Falling) You may have to adjust to the time. A circuit used in such a case is called a synchronous circuit.

A synchronous circuit temporarily stores changes in an input signal that occur between one rising (falling) time of a clock signal and the next rising (falling) time, and outputs the output signal at a later rising (falling) time. The operation is to change the value of the input signal to be the same as the value of the input signal. Typically, the circuits used do not track input changes of more than one degree between two consecutive clocks.

[Conventional technology]

There are various types of synchronous flip-flops used in clock-synchronized circuits, such as D Frisopflops, synchronous RS Frisopflops, and JK Frisopflops. Taking the D Frisopflop as an example, Third
Shown as shown.

In this figure, l is a D flip-flop (DFF) circuit as a synchronous circuit, and D flip-flop 1 outputs a signal input to the data (D) terminal from output terminal Q in synchronization with the rising edge of clock C. . That is,
If the D input is “H” at the rising edge of the clock, it is “H”.
'' is "L", outputs "L".

Therefore, as shown in the timing chart of FIG. 4, by inputting "H" to the D terminal, "H" synchronized with the clock C is output to the Q terminal. This means that the input state of data D at the rising edge of clock C is output to the Q terminal with a slight delay.

[Problem to be solved by the invention]

However, in such conventional synchronous circuits,
For example, as shown in Figure 5, if the "H" input to the D terminal is shorter than the clock cycle, the D terminal will be synchronized at the rise or fall of the clock C. The input is “L”
”, even if data D has an “H” period, only “L” is output to the Q terminal.In other words, for an input signal shorter than the clock period, an output synchronized with the clock is generated. The problem was that it could not be done.

If an attempt is made to synchronize an input signal with a shorter period than the clock cycle, a clock having a narrower pulse width and higher frequency than the input signal must be used, resulting in increased costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization circuit that can obtain an output signal synchronized with a clock even if the input signal is shorter than the clock cycle.

[Means to solve the problem]

In order to achieve the above object, the synchronous circuit according to the present invention has a first circuit in which an input signal including a signal shorter than a clock period is input to a data input terminal, and a clock signal is input to a clock terminal.
a second holding means in which the input signal is input to a data input terminal and an inverted clock signal of the clock signal is input to a clock terminal; It is provided with logic means to which the outputs of the holding means are input, and for calculating the logical sum of these outputs.

[Effect]

According to the invention, an input signal including a signal shorter than a clock period is input to its data input terminal, and the input signal is input to the first holding means to which the clock signal is input to the clock terminal. A second holding means is provided in which an inverted clock signal of the clock signal is inputted to a clock terminal, and the outputs of the first and second holding means are logically determined and outputted as an output of the synchronous circuit.

Therefore, even if an input signal shorter than the clock period is input and the output of the first holding means remains "L", the second holding means receiving the inverted clock signal is synchronized with the inverted clock by the inverted clock signal. Outputs “H”. As a result, even if an input signal shorter than the clock synchronization is input, synchronization of either the first holding means or the second holding means is required, and a synchronous circuit is realized by applying this logic. can.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of a synchronous circuit according to the present invention, and this embodiment is an example in which a D clip-flop is used as the synchronous circuit.

First, the configuration will be explained. In FIG. 1, 11 is a synchronization circuit that synchronizes the input signal with a clock C, and the synchronization circuit 11 is a first D clip-flop (first holding means).
12. Second D clip-flop (second holding means)
13, an OR gate (logic means) 14 and a third D flip-flop 15, each data (D) input terminal of the first D flip-flop 12 and the second D flip-flop 13 receives the same input. At the same time, the clock C is input to the clock terminal of the first D flip-flop 12, and the inverted clock C is input to the clock terminal of the second D flip-flop 13. The output X1 from the output terminal Q of the first D flip-flop 12 and the output X2 from the output terminal Q of the second D flip-flop 13 are input to the OR gate 14 and OR
After being subjected to OR logic at gate 14, it is inputted to the data (D) input terminal of third D flip-flop 15 as OR output X3. The clock terminal C of the third D flip-flop 15 is inputted, and the output terminal Q thereof outputs the output X4 as the output of the synchronous circuit 11 to the outside. That is, the same input signal is input to the first D flip-flop 12 using clock C and the second D flip-flop 13 using inverted clock C, and the outputs X1 and X2 of these clip-flops are ORed. The input to the gate 14 and its output X are input to the third D flip-flop 15 using the clock C, and the synchronous output X4
This is what you get.

In the above configuration, the waveforms of each part of the synchronous circuit 11 are
It will look like the figure. As shown in FIG. 2, when an input signal shorter than the clock period is input to the first D flip-flop 12 and the second D flip-flop 13, the first D flip-flop 12 is activated as described in the conventional example. For the same reason as the output X.

remains “L”, but the second D flip-flop 1
At the output X2 of 3, an "H" level synchronized with the inverted clock is obtained. Then, when xl and X2 are input to the OR gate 14 and the obtained output "H" output X4 is obtained.

Therefore, according to this embodiment, even if the input signal is shorter than the clock period, an output signal synchronized with the clock can be obtained, and necessary short input signals can be synchronized without using a high clock period. can. As a result, in the past, in order to synchronize input signals shorter than the clock frequency, the clock of the entire device in which the synchronization circuit was incorporated was raised, but according to this embodiment, the same clock as before is used. Since it is possible to synchronize with short input signals while using the device, it is possible to significantly reduce costs. Furthermore, this means that the present invention can be implemented without causing major design changes to conventional devices, and in addition to cost reduction, it can be applied to a wide range of applications.

Note that in this embodiment, the output X3 of the OR game 14 is input to the third D flip-flop 15, and the third D flip-flop 15 is synchronized with the clock C. It takes into consideration synchronization with the third circuit, and if it is not necessary, the third circuit
The D flip-flop 15 is not necessarily essential.

Further, in this embodiment, a D clip-flop is used as the clip-flop, but of course the present invention is not limited to this, and other clip-flops such as a JK flip-flop may be used. Furthermore, it is not limited to the OR gate 14 as long as it takes the logic of the first D flip-flop 12 and the second D flip-flop 13.

[Brief explanation of drawings]

Figure 1.2 is a diagram showing an embodiment of the synchronous circuit according to the present invention, Figure 1 is its overall configuration diagram, Figure 2 is a timing chart of each part, and Figures 3 to 5 are conventional synchronous circuits. FIG. 3 is a diagram showing a D flip-flop as a synchronous circuit, FIG. 4 is a timing chart thereof, and FIG. 5 is a timing chart when an input signal shorter than the clock cycle is input. It is. 11... Synchronous circuit, 12... First D flip-flop (first holding means), 13... Second D flip-flop (second holding means), 14...OR gate (logic means), 15...
...Third D Frisobfurosop. Fig. 1 Timing chart of each part of the embodiment Fig.

Claims (1)

[Scope of Claims] First holding means, wherein an input signal including a signal shorter than a clock cycle is input to a data input terminal, and a clock signal is input to a clock terminal; the input signal is input to a data input terminal; a second holding means into which an inverted clock signal of the clock signal is inputted to a clock terminal; and a logic into which the output of the first holding means and the output of the second holding means are inputted, and which takes the logical sum of these outputs. A synchronous circuit comprising means and.