JPH04186914A - Temporary holding circuit - Google Patents

Abstract

PURPOSE:To simplify hardware to offer the temporary holding circuit of low cost by supplying a clear signal to the reset terminal of a second D-type flip- flop, and setting the output of a second D-type flip-flop as a circuit output. CONSTITUTION:To a clock input terminal of a DFF2, the output 55 of this AND circuit 5 is applied, and a clear signal 40 is set as a reset signal of the DFF2. When the input signal of an input terminal 10 is '1', when a clock signal 30 rises, the Q output 25 of a DFF1 goes to '1'. As a result, when the next clock signal rises, the output 35 of the DFF2 goes to '1' and the output 20 of an AND circuit 3 goes to '1' at time both the Q outputs 25 and 35 of the DFFs 1 and 2 are both '1', it is inverted by an inverter 4, the clock signal 30 being one input of the AND circuits 5 is masked, and comes to a temporary holding state. Such a state is continued until the DFF2 is reset by the clear signal 40.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a temporary holding circuit, and more particularly to a temporary holding circuit that temporarily holds digital data.

Prior Art As a conventional temporary holding circuit of this kind, the circuit shown in FIG. 3 is widely used. A D-type flip-flop (hereinafter referred to as DFF) 1 uses an input signal at an input terminal 10 as a data input, uses a clock signal at an input terminal 30 as a clock input, and takes in and holds data input in synchronization with the rising transition timing of this clock signal. do.

The DFF2 uses the Q output 25 of the DFFI as a data input, and similarly takes in and holds the data input in synchronization with the rising edge of the clock signal.

AND circuit 3 is each Q output 25 and 35 of DFFI and 2.
is powered by two people, and the output 45 of this ant circuit 3 is DFF9.
This is a set input. The DFF 9 has "0" as its data input, and a clear signal 40 is applied to its clock input. The Q output 20 of this DFF 9 is the circuit output.

FIG. 4 is a timing chart showing the operation of the circuit of FIG. 3. If the signal at the input terminal 10 is "1" at the rising timing of the clock signal 30, the Q output 25 of the DFFI becomes "1", and when the next clock signal rises,
The Q output of DFF2 becomes “1”. In this way, DFF2
follows the operation of DFFI with a delay of one clock period.

When the Q outputs 25 and 35 of DFFI and 2 become "1" at the same time, the output 45 of the AND circuit 3 becomes "1°,"
The DFF 9 is set, and its Q output 20 becomes "1", resulting in a temporary holding state.

This temporary holding state is cleared when the clear signal at the terminal 40 becomes "0". Further, noise is removed by logically multiplying the outputs of DFFI and 2 by the AND circuit 3.

Since such a conventional circuit uses three DFFs, the circuit configuration becomes complicated and the cost becomes high.

OBJECT OF THE INVENTION Therefore, the present invention has been made to eliminate the drawbacks of the conventional example, and its purpose is to simplify the hardware and provide a low-cost temporary holding circuit.

Structure of the Invention The temporary holding circuit according to the present invention includes a first D-type flip-flop that captures and holds a data input signal in synchronization with the level transition timing of one of the clock signals, and a clock input terminal for the output of this D-type flip-flop. a second D-type flip-flop that captures and holds the signal in synchronization with the level transition timing of one of the signals applied to the signal; and an AND circuit that outputs the AND of the outputs of the first and second D-type flip-flops. , means for masking the clock signal in response to the AND output and applying it to the clock input of the second D-type flip-flop;
A clear signal is supplied to the reset terminal of the second D-type flip-flop, and the output of the second D-type flip-flop becomes a circuit output.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 3 are indicated by the same symbols. In this example, the third
In place of the DFF 9 shown in the figure, an inverter 4 that inverts the output 20 of the AND circuit 3 and an AND circuit 5 that outputs the logical product of the output of the inverter 4 and the clock signal 3o are used.

The output 55 of the AND circuit 5 is applied to the clock input terminal of the DFF 2, and the clear signal 4° is used as a reset signal for the DFF 2, and the other configuration is the same as that shown in FIG.

FIG. 2 is a timing chart showing the operation of the circuit of FIG. 1. When the input signal of the input terminal 1o is "1", when the clock signal 30 rises, the Q output 25 of DFF1 becomes "1".
”.As a result, when the next clock signal rises, DF
Output 35 of F2 becomes "1". Output 20 of AND circuit 3 becomes both Q output 2 of DFFI and 2.
5 and 35 are both "1", which is inverted by the inverter 4, and the clock signal 30, which is one input of the AND circuit 5, is masked.
The contents of FF2 are temporarily held.

This temporary holding state will continue until the DFF 2 is reset by the clear signal 4o.

For noise with a pulse width smaller than the synchronization of the clock signal, DFFI and 2 will not become "1" at the same time, so the noise is removed. That is, the circuit of this embodiment can perform temporary holding while removing noise, similar to the conventional example shown in FIG.

Effects of the Invention According to the present invention, since the number of DFFs can be reduced from three to two, there is an effect that a cheaper temporary holding circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the embodiment of the present invention, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is a diagram showing the operation of a conventional example. This is a timing chart. Explanation of symbols of main parts 1.2...DFF 3.5...AND circuit 4...Inverter

Claims (1)

[Claims] (1) A first D-type flip-flop that captures and holds a data input signal in synchronization with the level transition timing of one of the clock signals, and an output of this D-type flip-flop that receives one of the signals applied to the clock input terminal. a second D-type flip-flop that captures and holds data in synchronization with the level transition timing; an AND circuit that outputs a logical product of the outputs of the first and second D-type flip-flops; means for masking a clock signal and applying it to a clock input of the second D-type flip-flop; providing a clear signal to a reset terminal of the second D-type flip-flop; A temporary holding circuit characterized in that the output of the pump is used as the circuit output.