JPS6384347A - Generating circuit for phase detecting signal - Google Patents

Abstract

PURPOSE:To reduce the effects of signal distortions and carrier wave jitters and to decrease demodulating errors by setting the phase of a phase detecting signal at a level sufficiently apart from the phase changing point of the data carrier wave input. CONSTITUTION:The output 541 of a logic circuit 540 is inputted to a D input terminal 551 of a D type flip-flop 550. The output 515 of a T type flip-flop of a dividing pat 510 is inverted by an inverting circuit 560 for production of a signal 561. This signal 561 is inputted to a CK input terminal 552 of the flip-flop 550. The output signal 541 of the circuit 540 is delayed by the flip-flop 550 and outputs as a signal 554 through a Q output terminal 553. The signal 554 is used as a phase detecting signal. The delay value between signals 541 and 554 is equal to 1/2 clock of the Q output signal 515 of the flip-flop 516. As a result, the signal 554 is set at the center between the phase changing points adjacent to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a phase detection signal generation circuit applied to a modulation/demodulation device (referred to as a modem) in data communications.

A demodulation phase detection signal generation circuit is indispensable in a modem using a conventional phase keying method (hereinafter abbreviated as PSK). Third
The figure is a block diagram of a demodulation circuit used in a conventional general PSK modem, in which 1 is a timing extraction section;
2 is a phase detection section, 21 is a phase detection signal generation circuit block for PSK demodulation, 22 is a phase detection circuit block, and 3 is a decoder. FIG. 4 is a circuit diagram showing the configuration of the PSK demodulation phase detection signal generation circuit block 21 in FIG. 220, frequency division control section 230
and a logic processing circuit 240 as constituent elements.

The operation of the conventional general PSK demodulation phase detection signal generation circuit configured as described above will be described below.

FIG. 5 shows signal waveforms at various parts between the blocks in FIGS. 3 and 4.

First, the carrier wave 11 is input to the timing extractor 1 in FIG. The timing extraction section 1 extracts a modulated wave whose phase is modulated by full-wave rectification and bandpass filtering of the carrier wave 11. Furthermore, this modulated wave, which is an analog waveform, is converted into a rectangular wave by a zero crossing circuit to obtain a modulated timing signal (SYNC) 12. As shown in FIG. 5, the phase change point of the carrier wave 11 (arrow in FIG. 5) coincides with the midpoint of the "1" section of 5YNC12. This 5Y
The NC 12 is input to the PSK demodulation phase detection signal generation circuit 21 of the phase detection section 2 . In the PSK demodulation phase detection signal generation circuit 21, as shown in FIG.
20, the phase of 5YNC12 and the output 211 of the frequency divider 210 is compared.

The frequency relationship between the 5YNC12 and the output 211 of the frequency divider is f2=5+×20, where the frequency of the 5YNC12 is fl and the frequency of the output 211 of the frequency divider is f2.

When the phase of 5YNC12 is ahead of the outer circumference output 211, the output 221 of the phase comparator 220 causes the frequency division control section 230 to control the frequency division section 2 using one output 233.
10 T-type flip-flops from the first stage 215 to the nth stage 213 are initialized to shorten the period of the outer peripheral output 211.

On the other hand, if the phase of 5YNC12 is behind the outer peripheral output 211, the output 221 of the phase comparison section 220 causes the frequency division control section 230 to enter the set state, stop its input clock signal 231, and control the frequency division control section 230. the other output 23
2 is kept at a certain level (“1” or “O”), so the period of the output 211 of the frequency divider 21.0 becomes longer. Due to this effect, in the circuit shown in Fig. 4, 5YNC12
and the output 211 of the frequency dividing section 210 are synchronized. The phase detection signal 241 is obtained by ORing the output 211 of the frequency dividing section 210 and the inverted signal of the output 212 of the T-type flip-flop 214 of the frequency dividing section 210 using the logic circuit 240. Therefore, as shown in FIG. 5, the timing of the phase detection signal 241 changes from "O" to "1" at the point where 5YNC12 changes from "1" to "0".
The transition from 1" to "O" occurs at the midpoint between "0" and "0" of the NC 12. This phase detection signal 241 is input to the phase detection circuit 22 as shown in FIG. The detection signal 241 is counted by the pulse counting method over "1"1", and the data 301 is input to the decoder 3.

The decoder 3 decodes the phase detection result data 301. The above is the demodulation operation.

Problems to be Solved by the Invention However, as shown in FIG. 5, since there is no phase detection signal 241 at the center of adjacent phase change points, distortion components of the signal near the phase change points pass through the telephone line. , due to the group delay characteristics of the telephone line, it may reach the phase detection signal section, affecting phase detection. Furthermore, it has the disadvantage that there is little margin for carrier wave jitter due to passage through a telephone line, and there is a high possibility that demodulation errors will occur.

The present invention solves the above-mentioned conventional problems, and aims to provide a phase detection signal generation circuit for PSK demodulation with a simple configuration that reduces demodulation errors.

Means to Solve the Problem The phase detection signal generation circuit for PSK demodulation of the present invention uses the extracted 5YNC12 as a reference, and detects the phase at the farthest position from the phase change point, that is, at the center of the 0'' section of 5YNC12. It has a configuration for performing detection.

According to the present invention, by setting the phase detection signal to a phase sufficiently distant from the phase change point of the data carrier input, the influence of signal distortion near the phase change point and carrier wave jitter after passing through the telephone line can be eliminated from the phase detection signal. It is possible to prevent it from being fed inside. Therefore, this reduces waveform distortion when detecting the phase of the carrier wave, enables accurate phase detection by the pulse counting method, and improves demodulation performance.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a phase detection signal generation circuit for PSK demodulation according to an embodiment of the present invention.

510 is a clock frequency division section, 520 is a phase comparison section, 530
540 is a frequency division control unit, and 540 is a logic circuit. In this embodiment, in addition to these, a D-type flip-flop 550 and an inverting circuit 560 are added.

The operation of the phase detection signal generation circuit for PSK demodulation of this embodiment configured as described above will be described below. Frequency division section 510, phase comparison section 5201 frequency division control section 530
, the configuration of the logic circuit 540 and the outline of its operation are the same as those of the conventional example.

The output 541 of the logic circuit 540 is connected to the D-type flip-flop 5.
input to the D input terminal 551 of 50. The output 515 of the T-type flip-flop of the frequency dividing section 510 is inverted by the inverting circuit 560, and the resulting signal 561 is input to the CK input terminal 552 of the D-type flip-flop 550. The timing of these signals is shown in FIG. The output signal 541 of the logic circuit 540 is delayed by a D-type flip-flop 550 and output from its Q output terminal 553 to become a signal 554, which is a phase detection signal. The amount of delay between the signal 541 and the phase detection signal 554 is determined by the T-type flip-flop 51.
As a result, the phase detection signal 554 is located at the center between adjacent phase change points.

As described above, according to this embodiment, the logic circuit 540 is
By delaying the output 541, which corresponds to the phase detection signal in the conventional device, to the center between adjacent phase change points in the carrier wave, the influence of signal distortion and jitter on phase detection is reduced. can be reduced and demodulation performance can be improved.

Effects of the Invention As described above, according to the present invention, demodulation performance can be improved with an extremely simple circuit configuration, and it is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a phase detection circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of signals of each part, and FIG.
FIG. 4 is a block diagram of a conventional PSK demodulation circuit, FIG. 4 is a block circuit diagram of a conventional phase detection circuit, and FIG. 5 is a timing chart of signals of each part thereof. 550...D type flip-flop, 560...
...Inverting circuit, 551...D input terminal, 5
52... Clock input terminal, 553...
・Q output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person = 9-

Claims (1)

[Claims] A phase detection signal generation circuit comprising circuit means for generating a phase detection signal for demodulation in a phase modulation modulation/demodulation device with a phase relationship located at the center between adjacent phase change points in a carrier wave.