JPH0236631A - Bit phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To reduce the effect of dispersion in a gate delay time by ORing with a double clock and inverse of the double clock and using a clock so as to extract the signal being the result of ORing of the said outputs. CONSTITUTION:A clock inverse of 2ck and a data D1 are supplied to two input terminals of an AND gate 41 in an output gate extraction section 40 and a clock 2ck and a data D2 are given to two input terminals of an AND gate 42. Since the clocks 2ck, inverse of 2ck reach an H level alternately, the data D1, D2 are given to an OR gate 52 of an output section 50. Output signals DA, DB of the AND gates 41, 42 are signals being the result of synchronizing the H level of the input signal DI with the clock 2ck. Then the signals DA, DB inputted to the output section 50 are ORed by an OR gate 52, the result is a signal DD synchronously with the clock ck, the signal DD is extracted just in the center by using the clock, inverse of ck by a flip-flop 51 and the result becomes an output data DO. Thus, the effect due to the dispersion in the gates is avoided.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase synchronization circuit used in communication line devices of exchanges, etc., and in particular, the present invention relates to a phase synchronization circuit used in communication line devices of exchanges, etc. This invention relates to a bit phase synchronization circuit for signal reproduction.

[Conventional technology]

For example, a communication path device of an exchange is equipped with a phase synchronization circuit that adjusts the phase of each input signal in order to reproduce signals input with different phases according to a clock of the same frequency.

As shown in FIG. 9, the conventional phase synchronization circuit has a delay element 4.
, 5 create three clocks whose phases differ by τ, and the flip-flops 1, 2.3 capture the input signals with their respective clocks, and output the captured values SL, S2 . S3 is obtained (see Figure 10).

When the values of Sl and 82 are the same, it is determined that the input signal and the clock are in phase, and S2 is used as the reproduced output.

If S1≠82, the switch 6 is switched by a control signal to sequentially apply a delay of a fixed value to the input signal, and this is repeated until 51=82.

In addition, as related to the conventional phase locked circuit, 198
6 “International Zurich Seminar
Collected Papers on Digital Communication” C4, 1-C
4,4 (1986 International Zuti
ch Sem1ner on Digital Co
+umunicatons collection of papers C4,1-C4,4
).

[Problem to be solved by the invention]

In an exchange, a bit phase synchronization circuit is required for each line. Therefore, when configuring a large-scale system, it is necessary to incorporate the bit phase synchronization circuit into an LSI. In that case,
In the above conventional technology, since the input signal is delayed using an internal gate, it is necessary to take into account the variation in the propagation delay time of the internal gate, and in order to cope with the case where the delay time is the minimum, a large number of delays are required. A gate is required, and in order to cope with the maximum delay time, it is necessary to set the delay amount finely so that the delay interval does not become large. There is a problem with increasing scale.

An object of the present invention is to provide a bit phase synchronization circuit that is suitable for LSI implementation and is less affected by variations in gate delay time.

[Means to solve the problem]

In order to achieve the above object, the invention according to claim 1 includes a circuit that uses a clock having the same period as one bit of input data as a double period clock, and inputs the double clock and the opposite phase of the double clock. A flip-flop that punches out data at the rising edge and falling edge of the data, an AND gate that ANDs the double clock and the opposite phase of the double clock, and the output logic of the flip-flop and the AND gate. In addition, two flip-flops other than the flip-flops are provided.
The output of the OR gate is connected to this set input, and the outputs of the two flip-flops are ANDed with the double clock and the opposite phase of the double clock, and the outputs are combined with each other. A bit phase synchronization circuit is constituted by an output circuit section having another flip-flop which punches out the logical sum signal using a clock.

Further, in the invention as claimed in claim 2, n clocks having the same clock period but shifted by 1/n phases are created.
The n-phase clock is connected to each data input terminal, and the n-phase clock is connected to each data input terminal. a data phase determination circuit that commonly connects a start signal and receives clocks of each phase at the rising edge of input data and determines whether the rising edge of the data is between the rising edge of the clock of which phase and the rising edge of the phase clock; It is equipped with a selection gate circuit and a flip-flop that selects one of the n-phase clocks according to the result of the data phase determination circuit, and its data input terminal is connected to input data, and its clock input terminal is connected to the output of the selection gate circuit. a data delay circuit that delays the input data for a certain period of time by punching the input data with a clock of a certain phase according to the result of the data phase determination circuit; and a data delay circuit that punches out the data delayed by the data delay circuit using a taro clock to generate output data. A bit phase synchronization circuit is constructed with the output section.

[Effect]

In the bit phase synchronized circuit according to claim 1, the clock is set to 2.
The period is doubled, the clock pulse width is made the same as the 1-bit width of input data, and this doubled clock is output as follows instead of input data having jitter etc.

When the input data is rHJ, the "H" pulse of the double clock When the input data is "L", the "L" pulse of the double clock To do this, detect the phase relationship between the input data and the double clock. Is the input data "H"?

It is necessary to determine whether it is "L".

In order to know the phase relationship between the input data and the double clock when the input data changes, we use the opposite phase of the double clock and the double clock as the rising edge of the input data.

Punch out each flip-flop on the falling edge. In order to know the overlapping state of the input data and the rJ pulse and the [H] pulse of the double clock, or the r]=J pulse and the "L" pulse, we calculate the AND of the double clock and the input data, and The logical AND of the reverse phase of the double clock and the negative phase of the input data is performed using an AND gate.

Then, the output of the flip-flop and the output of the AND gate are logically summed as follows using an OR gate.

If the "H" pulse of the double clock and the rising edge of the input data rl (J pulse) overlap, the double clock is taken in at the rising edge of the input data.In this case, the output of the flip-flop becomes unstable, but The output of the AND gate that checks the overlapping state of the double clock and input data is rHJ.

At this time, the AND gate output side is used. Furthermore, when the rising edge of the input data "H" pulse comes at the end of the "H" pulse of the double clock, there is almost no overlap between the double clock and the input data (it becomes "L", but the flip The output of the flop can take in the rH'' pulse of the double clock.In this case, the output side of the flip-flop is taken.

By doing so, even if the phase relationship between the input data and the double clock is arbitrary, the positional relationship can be made clear.

In addition, even if there is noise such as jitter in the input data and this overlaps with the change of the 2-bit clock, a flip-flop circuit that makes judgments at the change of the rising and falling edges of the input data and the level of the input data. The positional relationship can be clarified using either of the AND gates that determine the (overlapping state), and the influence of jitter, etc. of input data can be removed.

The flip-flop using the "H" pulse of the double clock and the flip-flop using the "L" pulse are set by the output of the above-mentioned OR gate containing the "H" information of the input data, and the flip-flop uses the "H" pulse of the double clock. It is reset by the output of the OR gate containing "L" information.

Therefore, the output of this flip-flop is:

The output corresponds to changes in input data. This flip
By taking the AND of each output of the flop with the double clock and the opposite phase of the double clock, the rH" pulse and "L" pulse of the double clock are obtained instead of r) (J, rlJ of the input data. It becomes possible to use

Furthermore, the logical sum of this output is taken and the flip/flip for data reproduction is performed.
By using this as an input to a prop and punching it with a clock, output playback data can be obtained.

In the bit phase synchronized circuit according to claim 2, the data phase determination circuit punches out the tarok of each n phase at the rising edge of the starting signal outputted from the starting circuit in synchronization with the rising edge of the input data, and checks the clock of each n phase. Latch the level. The level QQ of the latched Q-phase clock and Q+1
The opposite phase of the level of the phase clock (the AND of 1+1 is rl(
Two clocks Q, +2+1, which are J, are detected, and it is assumed that there is a rising edge of data between the two detected clocks, and the data is punched out in the output circuit.

At this time, the data is delayed by the data delay circuit using the aforementioned flip-flop so that the clock passes through the midpoint of the 1-bit width of the data. The delayed data is recovered near the midpoint by the clock, thereby making it possible to recover input data containing jitter.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a bit phase synchronization circuit according to an embodiment of the invention as claimed in claim 1. This bit phase synchronized circuit includes a double clock generation section 10, a data generation section 20, a data generation section 30, an output data extraction section 40, and an output section 5.
Consists of 0. The double clock generation unit 10 converts the clock ck into two times the clock ck using the flip-flop 11.
A clock 2ck having twice the period and a clock 2ck having an opposite phase to the above 2ck are created. The data creation unit 20 and the data creation unit 30 input data and the 2ck.

Create output data information from 2ck. The output data extraction section 40 extracts the clock 2ck from the output data information of the data creation section 20 and the data creation section 30.

2ck extracts data and sends it to the output section 50. The output unit 50 re-inputs the data sent from the output data extraction unit 4o using a clock ck having an opposite phase to the clock ck, and outputs data D.

shall be.

Next, the operations of the data creation section 20 and the data creation section 30 will be explained using FIGS. 1 and 2.

FIG. 2 is a time chart showing the period until data input at a certain phase is output from the data creation section 20.

The 2ck is connected to a data input terminal of a flip-flop (hereinafter referred to as FF) 21, and input data DI is connected to a clock terminal and a reset terminal. Said 2ck
is "H", when the input data rises, FF21
The output Q1 becomes rHJ, and when the input data becomes rJ, a reset is applied and the Q1 becomes "L". 2ck is connected to one input terminal of the AND gate 23 like the data input terminal of FF21, and DI like the clock input terminal of FF21 is connected to the other input terminal, and when both 2ck and DI are rHJ, the output A1 is "H". becomes. noah gate 2
Ql and A1 are connected to the input terminal of 5, so when the output S1 of the NOR gate 25 is "L", 2ck is r) (
J indicates that the data rises or the data is also "H". The data input terminal of F22 has F
2ck is connected like FI, the inverted DI of input data DI is connected to the clock terminal and reset terminal, and 2ck is "
When the input data falls, the output Q2 of the FF 21 becomes "H", and when the input data becomes rHJ, a reset is applied and Q2 becomes "L". 2ck and DI input to the FF 22 are connected to two input terminals of the AND gate 24, respectively, and when both 2ck and DI are at "H", the output A2 becomes "H". noah gate 2
Q2 and A2 are connected to the input terminals of the NOR gate 26. Therefore, the output R1 of the NOR gate 26 indicates information that the data falls or is "L" when 2ck is "H". The 5RFF 27, in which S1 is connected to the set terminal and R1 is connected to the reset terminal, outputs a signal D1 containing information of one bit width or more of every other bit of input data (hatched).

FIG. 3 is a diagram illustrating the operation of the data creation section 30 when the same data having the same phase as that in FIG. 2 is input. The 2ck is connected to the data input terminal of the flip-flop (FF) 31, and the input data DI is connected to the clock terminal and reset terminal. When the 2ck is "H" and the input data rises, the FF31 Output Q3 is rHJ
When the input data becomes "L", a reset is applied and Q3 becomes "L". Similar to the FF31, 2ck and DI are connected to the input terminal of the AND gate 33, and 2c
When both k and DI are "H", the output A1 becomes r HJ. The above Q3 and A3 are input to the Noah gate 35,
The output S2 of the NOR gate 35 becomes rLJ indicating that the data rises when 2ck is "H" or that the data is also "H". 2ck is connected to the data input terminal of FF32 like FF31, and the above-mentioned DI is connected to the clock terminal and reset terminal. When 2ek is rHJ and the input data falls, the output Q4 of FF32 becomes rl(J). When the input data becomes "H", a reset is applied and the Q4 becomes "L".The two input terminals of the AND gate 34 have 2ck and D
When I is connected and 2ck is r HJ, DI is r HJ
If so, the output A4 of the AND gate 34 becomes "H". The two input terminals of the NOR gate 36 are connected to the Q4A4, respectively, so that the output R of the NOR gate 36 is connected to the two input terminals of the NOR gate 36.
2 outputs "H" when the input data is rI, J when 2ck is "rH". The above S2 is connected to the set terminal of the 5RFF 37, and the above R2 is connected to the reset terminal, and information D2 having a level of one bit or more of the input data, which is subjected to hunting, is output.

Next, according to FIG. 4, the data creation section 20. The output data extraction unit 4 extracts Di and D2 output from the data creation unit 30.
0 as data synchronized with the clock,
An output signal is output from the output section 50.

The operation up to this point will be explained. In the output data extraction section 40, 2ck and Dl are connected to two input terminals of an AND gate 41, and 20 and D2 are connected to two input terminals of an AND gate 42. 2ck and 2ck
is alternately r HJ, so the signals Di and D2 are alternately input to the OR gate 52 of the output section 50. The output signals DA and DB of the AND gates 41 and 42 are signals obtained by synchronizing the rH level of the input signal DI with the clock 2ck, as shown in FIG. In the output section 50, the input signals DA and DB are combined by an OR gate 52 to become a signal DD synchronized with the clock ck. This signal D
D is punched out exactly in the middle by the reverse phase clock ck of the clock ck by the FF 51, and becomes output data D○.

FIG. 5 is a configuration diagram of a bit phase synchronization circuit according to an embodiment of the invention as claimed in claim 2. This bit phase synchronized circuit includes a three-phase clock generation section 60, a start signal generation section 70,
It consists of a data phase determination section 80, a data delay section 90, and an output section 100. The three-phase clock generation unit 6o uses the clock ck to generate clocks ckl and c that are shifted by 1/3 phase.
Create k2゜ck3. The activation signal generation unit 7o generates the activation signal DI' in the flip-flop 71 in synchronization with the rise of the input signal DI. In the data phase determining section 80, each of the clocks ckl, ck2 . c.
Flip-flops 81, k3 are connected to their respective data inputs, and the clock terminals are commonly connected to the above-mentioned DI'.
82.83, the level of each clock is taken in at the rising edge of data. The outputs Ql, Q2 . Q3, its inverted output Ql, Q2 . Q3 is AND gate 84°85.
86. The two input terminals of the AND gate 84 are connected to the Q1 and Q2, and the two input terminals of the AND gate 85 are connected to the two input terminals of the AND gate 84.
The two input terminals of the AND gate 86 are connected to the above-mentioned Q2 and Q3, and the two input terminals of the AND gate 86 are connected to the above-mentioned Q3 and Ql.
and ck2, ck2 and ck3,
Depending on whether it is ck3 or ckl, one of the AND gates 84, 85, and 86 is made to output rHJ. In the data delay unit 90, input data is delayed by a data delay flip-flop (DFF) 94 according to the output of the AND gate 84°85.86 of the data phase determination unit 80. , the delayed input data is reproduced by a clock and used as output data.

Figure 6 shows human input data at a certain phase.

FIG. 3 is a diagram illustrating an operation up to being output as output data synchronized with a clock.

Now, in the input data DI that has entered with a certain phase, DI' is output from the start signal generation section 70 in synchronization with the rising edge of the input data DI as the clock of the flip-flops 81, 82, 83 of the data phase determination section 80. The level of each clock is sent to the flip-flops 81 and 8.
2.83 output terminals Ql, Q2. Output to Q3. Second
At the phase of the input data shown in the figure, the outputs of each flip-flop 81, 82, 83 are Q1=H, Q2=L,
Q3=H. Then, the output S2 of the AND gate 85 having Ql and Q2 as input terminals becomes "H", and Q2
．． The output S3 of the AND gate 86 having Q3 as an input terminal becomes "L", and the output S1 of the AND gate 84 having Q3°Ql as an input terminal also becomes "L". Based on this result, it is determined that the rising edge of the input data DI has a phase between ckl and ck2. Then, one of the input terminals of the AND gate 91 of the data delay section 90 becomes "H", the clock ck3 is output as the output G2 of the AND gate 91, and the input data is reproduced by the above ck3 in the flip-flop (DFF) 94. This is used as delayed data DQ, and the flip-flop 102 in the output section 100 creates data DO synchronized with the clock ckl.

Next, as shown in FIG. 7, Sl, S2 . The relationship between the value of S3 and the operation of the data delay section 90 will be explained.

FIG. 7 shows input data DI(1),
This indicates that DI (2) and DI (3) have been input. Since the input data DI (1) is in the same phase as the input data DI shown in FIG. 6, 5L=L, 52=H,
53=L, and is reproduced by the clock CK3 by the DFF94 of the data delay unit 90, and becomes DQ (1),
In the output section 100, it is reproduced by the flip-flop 102 as ckl and becomes DQ(1). Input data DI
(2) is 51=L, 52=L, 5 in the above algorithm.
3=H, one of the input terminals of the AND gate 93 of the data delay section 90 becomes rHJ, and the input data DI (2) is output as the output G1 of the AND gate 93. Input data D output from AND gate 93
I (2) is the FF 102 in the output section 100.
It is reproduced by ckl, resulting in DQ(2). The input data DI (3) is 51=H, 52 according to the above algorithm.
=L, 53=L, one of the input terminals of the AND gate 92 becomes "H" in the data delay unit 9o, the clock ck2 is output from the AND gate 92, and the human data is inputted by ck2 in the flip-flop 94. He was overtaken and became a DQ (3).

Then, in the output section 100, the flip-flop 1
At 02, it is reproduced by ckl, resulting in Do (3). As a result of the above, as shown in FIG.
I (1), DI (2), and DI (3) are output data D synchronized with taro clock ckl.

(1), DQ (2), and Do (3).

Next, the jitter absorption rate in this example will be explained with reference to FIG. Input data DI■, D shown in FIG.
I■ indicates a range G of input data in which the rising edge of data falls between clocks ckl and ck2, and data in this range is punched out by ck3 in the flip-flop 94 in the data delay section 90. In both cases of DI■ and DI■, even if the 1/3 cycle data deviates in the worst case, it is possible to punch out with ck3 without error.

According to this embodiment, if the input data contains jitter within ±1/3 cycle, it can be reproduced without error. Furthermore, since the number of gates is small, it is suitable for LSI implementation.

〔Effect of the invention〕

According to the invention as claimed in claim 1, since input data can be reproduced without delaying the data clock, it is less susceptible to gate variations, has excellent followability to signal speed, and can be input at different phases. The incoming data can be played back in synchronization with the clock. Furthermore, since it does not include a delay element, it has the ability to follow the signal speed, and has the effect of being able to reproduce input data with different bit rates simply by changing the bit rates of the input data and clock.

Further, according to the second aspect of the present invention, input data that is input at an arbitrary phase and includes jitter can be reproduced as data synchronized with a clock, and the number of gates can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bit phase synchronization circuit according to an embodiment of the invention as claimed in claim 1, and FIGS. 2 and 3. Figure 4 is a timing chart explaining its operation, and Figure 5 is a timing chart explaining its operation.
The figure is a block diagram of a bit phase synchronized circuit according to an embodiment of the invention as claimed in claim 2, FIGS. 6, 7, and 8 are timing charts for explaining its operation, and FIGS. 9 and 10 are FIG. 2 is a diagram illustrating a conventional bit phase synchronization circuit. 10... Double clock creation section, 20. 30... Data creation section, 40... Output data extraction section. ! 50, 100... Output section, 60... 3-phase clock generation section, 70... Starting signal generation section, 80... Data phase determination section, 90... Data delay section, 11.21, 22 ,31,32,51,71,81,8
2゜83.94,102...D flip-flop,
23.24,33,34,41,42,84,85,8
6゜91.92.93...and gate, 25.26
,35.36...Noah Gate, Hyaku1dake Yo δ3 Gi Tomoe R1
and 8 plot. Do (3) Collection diagram - T dimension diagram

Claims (1)

[Scope of Claims] 1. In a bit phase synchronization circuit that synchronizes the phase of a data signal input at an arbitrary phase with a clock, a circuit that converts a clock having the same period as one bit of input data to a clock with twice the period; A flip-flop that punches out the double clock and the opposite phase of the double clock at the rising and falling edges of input data, respectively, and an AND gate that performs logical AND with the double clock and the reverse phase of the double clock, respectively. , an OR gate that takes the logical sum of the outputs of the flip-flop and the AND gate is provided, and two flip-flops other than the flip-flop are provided, and the set input/reset input is connected to the OR gate. Connect the outputs of the two flip-flops, and further logically OR the outputs of the two flip-flops with the double clock and the opposite phase of the double clock, and then punch out the signal obtained by ORing the outputs with each other using the clock. A bit phase synchronized circuit consisting of an output circuit having another flip-flop. 2. In a bit phase/synchronization circuit that synchronizes the phase of data signals input at any phase using a constant clock, the clock period is the same but the phase is shifted by 1/n.
It is equipped with an n-phase clock generation section that creates 1 clocks, a startup circuit section that creates a startup signal synchronized with the rising edge of input data, and n flip-flops. a data phase determination section that determines at which position of the n-phase clocks the rising edge of data is; a selection gate circuit that selects one of the n-phase clocks based on the result of the data phase determination circuit; and a flip-flop. A bit phase synchronization circuit comprising: a data delay circuit having an input terminal connected to input data and a clock terminal connected to the output of the selection gate circuit; and an output section for resetting data delayed in the data delay circuit with a clock.