JPS59215158A - Demodulating circuit of dpsk modulating signal - Google Patents

Abstract

PURPOSE:To stabilize demodulating operation by forming a carrier signal without using a phase control loop and a multilication circuit to simplify the constitution and reduce the adjusting position. CONSTITUTION:Reference signals G, K phase-locked to a carrier wave of a modulation signal are formed in the timing shifted by each prescribed time from each phase change point of an inputted DPSK modulation signal; and a phase comparator circuit 7 compares the phase between the signals G, K and the modulation signal. Further, the output of the circuit 7 is sampled by a data clock C generated in synchronizing with a phase changing point detecting output at the center of each data section to reproduce sequentially the data. Thus, a phase control loop and a multiplication circuit are not required, thereby simplifying the constitution, and since each section consists of a digital logical circuit, the adjusting positions are decreased and a stable demodulating operation is realized.

Description

[Detailed description of the invention] (a) Industrial application field The present invention is applied to DPSK (D
iferential Phase 5hift K
eying) It relates to a demodulation circuit for a modulated signal.

(b) Prior art In general, PSK modulation uses binary data to phase-modulate the carrier, but one type of modulation, DP8, modulates the phase of the data at each end of one data period according to the content of the data in that period. ,
The phase of the carrier in the next data section is changed sequentially.

For example, in 4-phase DPSK modulation, 2 bits of serial data, ie 1 bit, are set as 1 data section, and the next section is determined according to the data content of this 1 section, ie, oo, oi, 1i, 10. 111] is delayed by the phase shift amount shown in the table below (also, demodulation of PSK modulated signals is conventionally performed by synchronous detection, so the carrier for synchronous detection (? It is necessary to extract the carrier signal from the modulated signal, but the extraction K of this carrier signal is
A method using Fi multiplication is generally adopted and is a more stable synchronous carrier? If required, use a synchronous oscillator at P
I was trying to use it by controlling L L il J.

However, in the above method, in the case of multi-phase D P S K4, the multiplication operation is repeated (in the case of 4-phase, multiplication by 4,
(In the case of 8-phase, it must be multiplied by 8), which increases the number of adjustment points and parts.Furthermore, it requires a filter for the multiplier circuit and PLL circuit, so it is not possible to complete the complete LS of the circuit.
The drawback was that it was difficult to integrate.

(c) Purpose of the Invention The present invention has been made in view of the above points, and is suitable for LSI implementation without necessity. The purpose of this paper is to propose a code demodulation circuit for DPSK modulation.

(2) Structure of the Invention An uninvented demodulation circuit creates a reference carrier signal whose phase is shifted by a certain period from each change point of the phase of a DPEIK modulated signal, and synchronizes this carrier signal with the modulated signal. The output is sampled at approximately the center of each data section using a data clock that is synchronized with the phase image/conversion point detection output of the modulation signal, and thereby the data in the previous e-pi-variant V4 signal is sampled. This is a configuration designed for playback.

(e) Embodiment FIG. 1 shows a demodulation circuit for a four-phase ILP SK modulated signal as an embodiment of the present invention, and this circuit will be explained below with reference to the signal timing diagram of FIG. 2.

In the first factor, (1) is the input terminal for the modulation signal to the received four-phase DF8, and the above-mentioned change 1llll from this terminal
II is given to the phase change point detection circuit (21).

This detection circuit t2H: Since the LDPSK modulated signal is generally band-limited and the transmission is exhausted, the amplitude changes greatly at the ψ point of the carrier phase.
! , l is used to detect the 'I' voice. On the contrary, the change point detection output is used to detect the 8 of the data clock.
A counter (4) which divides the output of the first crystal oscillation circuit (w; ta) selected to double the frequency by i is reset.

In addition, the binarization circuit (5) K consisting of a comparator, etc. is also input and is formatted into 2 (fffl), and the DPSK after the formatting Under the signal,
This is given to jF as DPSKli number) is given to reset pulse generation [01 path (mark) and phase comparator circuit (ヱ). Assuming that the modulation '2! is on, the DPSK Gogo from the binarization circuit +51 is CB) in the same figure, and the data (A) is output from the counter (4) mentioned above.
A data clock (C) equal to 0 will be output from the counter (4). Clock (0
The rising edge of ) triggers the 611st stage side of the two-stage connection σ) monostable multivibrator t81t9+, and the output of the previous stage side (Dl causes the subsequent stage side to trigger ζ, so the output from this latter stage is A pulse fEl of a constant width of ('l'1) is output manually in the Teichita Ward 1 White, and the pulse (E) of this (σ) is the D P S K from the binarization circuit (5). 'l^ issue (1iD-FF by El
(D flip clock) (By turning the sampling field at IOI, we get the second reset pulse (Fl %') as the output of this (7) FF. On the other hand, +1Dij
DP S K I, who's number, l! ! ,, the second crystal oscillation is selected to have a frequency of 8 times the number of quasi-carrier cycles, and this excavation output is T' -F Fd et al. and the second 'jA 3 D -F F' of the link connection. tl:1lI1
By dividing the frequency by 41 P, the 2nd D-F FII3117) output is the first dark gear +Gl, and the 5th D-
Taking the output of the F F' circle, the second reference carrier information (Ki
is obtained. At that time, the above F F 112i = I1
4: is reset at the fall of the litno (F') from the first D-FFII (1), so as shown in the figure, the first Sugisho carrier eye 6
No. (G) is in phase with the carrier of the DP SK signal from the reset to the end of the 1st section, 1st section, and the second
The reference carrier signal (K) is the first reference carrier signal (
The phase is delayed by 90° compared to G).

Part 1, Part 2, ■1 Carrier number (ol (K) is II
The phase comparator circuit (E1) constitutes the fourth and fifth D-F.
F (16iQ71), which can be applied as each clock of the
is sampled at each rising edge of the carrier signal (Gl (Kl). Therefore, this fourth D - F
The output of Ff161 is 5th D -F' in Fig. 2 (L).
The output of F'G7+ is 1 figure (M), and each output (L) (Ml is the next 6th 7th D -F y (181
At f191, the sampling I is performed again at the rising edge of the data clock (0) from the itl kawanta (4).
tt, its 16D-FF081 output (Pl and 7th D
-FF' (191 outputs (Q,) are obtained.

Cocote, PI lie phase comparison episode v! 6+71-t'
D P S K (No. 3 (B) and +if! 1 second reference carrier conversion No. (G) (Kl phase ratio IP! 2 is being performed, so one is the same frequency as the carrier of DPSK No. This is because if phase comparison is performed with two reference signals that differ by 90 degrees, it is possible to detect the phase changes in the four traces described above.

The reason why each comparison output (sampling output) is re-sampled at the rising edge of AT is due to the following reason. That is, the DPf4 signal is The tatami width has changed greatly, and for this reason, the phase of the carrier is not detected as a positive value near the changing point, but there is a time of 5't71, so it is far enough away from the changing point and in the center of the 1 data interval. This is to extract only the phase comparison output of the section.

Therefore, the sixth group 17D of the phase comparison path 11 (e)
-F'? (181 (Each output P of episode 1) (Looking at Q and l, the result of phase comparison for dibit ■t is 1
．． The phase comparison result for dibit ■ appears at time t2, and similarly, the comparison result for m2 diagram (Al valley data section +?+J appears with a delay of 6 bits. Then, this parallel comparison output CP1 (QI
U, for example, in the period t to t2 corresponding to dibit ■, P = Q = ``0'', and in the period t2 to t3 corresponding to dibit ■, the original is P = ``0'', Q, = ``1''. It is exactly opposite to the data of , and A is twice as long. Therefore, both outputs (Pl , the original data (Δ) can be restored.

Above, we have explained an actual example of a signal in a 4-phase DP61, but other multi-phase DPs such as 2-phase or 8-phase etc.
The case of sx4g can also be realized in the same way, in which case the reference carrier signal is determined by increasing the number of sampling circuits and leakage according to the power, and the reference carrier is two-phase. In case of 8 phases, 4 types of glaze are required.

Also, ge! If the frequency of the distorted DPSK signal is very high and it is difficult to directly perform digital processing as in the above practical example, the i' tuning signal can be converted to an appropriate intermediate frequency signal at once. This can be achieved by performing processing similar to 1111 after the weather has cooled down.

(f) Effects of the Invention According to the demodulation circuit of the present invention, there is no need for a phase control loop or a multiplier circuit for reproducing the carrier signal from the DPSK modulated code, so compared to the conventional demodulation circuit. The configuration is simple, and since each part can be implemented using digital logic circuits, a well-defined demodulation operation can be realized with a small number of elements D[. Since the phase control loop and the filter associated with the multiplier circuit are not required, it is suitable for complete LSI implementation of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a detailed example of a demodulation circuit according to the present invention, and FIG. 2 is a timing diagram of each part thereof. fil: DPSK modulation signal input terminal, (2
1: Phase change point detection circuit, f41: 4-bit counter, 151: Binarization circuit, +31tll: 1st and 2nd crystal oscillation circuit, Hiki): Reset pulse generation circuit,
(Engineering): Phase comparator circuit, +151: -! -8 Frequency divider circuit, 1201: Tecoder.

Claims (2)

[Claims] (1) A circuit that demodulates a DPSK modulation signal in which the phase of the carrier changes by a predetermined phase shift amount every one data interval, and the timing is shifted by one foot time from the input ζi or each phase change point of the DPSK modulation signal. Create a reference carrier signal 1 whose phase is synchronized with the carrier of the modulated signal, and compare the phase of this carrier signal with the modulated signal #? The data is sequentially reproduced by sampling the phase comparison output at approximately the center of each data section using a data clock generated in synchronization with the phase change point detection output of the modulated signal. Demodulation circuit for DPSK redundant signal. (2) The means for creating each reference carrier is the output of a reference transmitter selected at a frequency that is N times (N is a positive integer) the carrier of the modulated signal? 2. A demodulating circuit for a modulated signal in a DP8 according to claim 1, characterized in that the frequency dividing circuit divides the frequency by i in response to the data clock.