JPS5974757A - Detecting circuit of synchronous signal - Google Patents

Abstract

PURPOSE:To increase the detecting accuracy of a synchronizing signal, by detecting synchronizing signals of odd and even orders out of the parallel signals of odd and even orders obtained after demodulation of a 4-phase PSK signal. CONSTITUTION:The digital signal modulated by a 4-phase PSK system is demodulated and delivered in parallel to the signals of odd and even orders. Then these signals pass through an LPF2 and a waveform shaping circuit 3, and therefore synchronizing signals 9B and 9C of odd and even orders are delivered in parallel to each other. The signals are fetched into a shift register 22, and synchronizing signals are detected by synchronizing signal pattern detecting circuits 23 and 24 of odd and even orders respectively. Then the signal of ''1'' is fed to a double input AND gate 25 from each of the circuits 23 and 24, and a signal is delivered through a synchronizing signal detection output terminal to show the detection of a synchronizing signal of ''1''.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a PCM reproducing device, and particularly to a synchronization signal detection circuit suitable for detecting a synchronization signal from a digital signal modulated by a four-phase PSX method.

[Prior art]

When transmitting digital data, several pieces of data are grouped together to form a block, and in order to detect the beginning of the data block, a synchronization signal is inserted before the data block.
The transmission method is often used. An example of its configuration is shown in Figure 1. At this time, the receiving system must first detect a synchronization signal in order to obtain the original data block.

Here is a second diagram of the circuit that detects the synchronization signal.
As shown in the figure. In this figure, 1 is the digital signal input terminal of FIG. 1, 2 is a low-pass filter, 5 is a waveform shaping circuit, 4 is a rising and falling edge detection circuit in the transmitted digital signal, 5 is a crystal oscillator, 14 is a decoder, 6A is the output of the crystal oscillator, 7 is the counter, 8A is the output of the decoder 7, 9A is the output of the waveform shaping circuit 3, 10
11 is a 6-stage shift register, 11 is a sync signal pattern detection circuit, 12 is a 6-manual AND gate, and 15 is a sync signal detection output terminal.

Next, the operation of the circuit shown in FIG. 2 will be explained using the timing chart shown in FIG. The symbols on the left side of FIG. 5 correspond to the symbols marked in FIG. 2, and the timings of the signals are shown in the figure.

First, the signal shown in FIG. 1 is input to the digital signal input terminal shown in FIG. At this time, Den.

Since the waveform of the digital signal is distorted due to the characteristics of the transmission system 2, it is passed through a low-pass filter 2.

Thereafter, the waveform shaping circuit 3 shapes the waveform into a waveform similar to the original waveform. Next, put the rice in the shift register 1o.

3 When the synchronization signal pattern shown as an example in FIG. 9A comes in, a signal of "1" for each bit is input from the synchronization signal pattern detection circuit 11 to the 6-person AND game) 12, and the synchronization signal detection output terminal A signal of 1 is output from. However, if there is a delay or advance in the signal due to time fluctuations in the transmission system, an incorrect synchronization signal may be sent to shift register 1o.
may enter. In order to prevent this, it is sufficient to input the signal into the shift register 1o in the middle of the minimum pulse width T of the transmitted signal. For this purpose, in the example shown in Fig. 2, a crystal oscillator 5 is used so that a pulse of 8 crotres I enters within the minimum pulse width T, and its output 6A is input to the counter 7, and the output of the counter is 14N. and'12
The output 8A is decoded by the decoder 14 so that a pulse is output at 91. The output 8A is used as a clock for the shift register 1o, and the signal is input into the shift register at the 4th clock out of 8 clocks. The rising and falling edges of are detected by the edge detection circuit 4,
The output pulse clears the counter 7. Therefore, by outputting a pulse of 8A from the decoder 14 at the fourth pulse of 6A from the edge of FIG. 3, 9A, the shift register 1
A signal can be input to 0.

Also, if two or more of the same signal '0' or '1' are input in succession, the decoder will output a pulse again every 8th pulse from the previous pulse output from the decoder, so there is no need for any modification. The signal is shift register jOVc
enter.

Next, consider a case where four-phase PSK is used as a digital signal transmission method. An example of the circuit configuration at this time is shown in FIG. Here, the same reference numerals as in FIG. 2 have the same functions as in FIG. 2. Furthermore, 15 is a 4-phase psx signal input terminal, 1
6 is a multiplier, 17 is a carrier regeneration circuit, 18 is a phase shifter,
20 is an inverter, 21 is a two-stage shift register, 8i"
The output of the i-decoder 14, 9B is an odd-order signal output from the waveform shaping circuit 3, 9C is an even-order signal output from the waveform shaping circuit 6, and 19 and 4 are signals input in parallel by the shift register 21. This is a signal obtained by converting 9B and 9C into serial.

Next, the operation of the circuit shown in FIG. 4 will be explained using the timing chart shown in FIG. The symbols on the left side of FIG. 6 correspond to the symbols marked in FIG. 4, and the timing of the signals is shown in the figure. Further, arrows 19A, 9B, and 9C in FIG. 6 indicate the correspondence between parallel signals and serial signals.

The 4-phase p input to the 4-phase PSK signal input terminal 1 in Figure 4
The signal modulated by the 5x method is demodulated by the 4-phase PSK demodulation circuit pressure of the multiplier 16, the carrier signal regeneration circuit 17, and the phase shifter 18, and is passed through the bandpass filter 2 and waveform shaping as odd-order and even-order signals, respectively. After entering the circuit 3, signals 9B and 9C are output, respectively. At this time, if the above-mentioned synchronization signal detection method is used, the shift register 21 must convert the unbalanced signals 9B and 9C into the serial signal 19A. Furthermore, even if edge detection is taken from signal 9B, the output of the decoder 14 must be like signal 8B, and at this time, the time fluctuation margin is iT for advance and 17 for delay. There is no Tl-, unchanged from the previous example. Further, the resolution is only 8 equal parts of the pulse width T.

[Object of the Invention] An object of the present invention is to improve the margin for time fluctuations in the timing of signal acquisition compared to the conventional example when detecting a synchronization signal after demodulating a digital signal modulated by the 4-phase PSX method. Furthermore, it is an object of the present invention to provide a synchronization signal detection circuit that improves the detection accuracy of synchronization signals by capturing signals at finer timing with respect to the minimum pulse width of the signal.

[Summary of the invention]

The odd-order and even-order parallel signals demodulated by the 4-phase PSH demodulator are not converted into serial signals, but are kept parallel, and the synchronization signals are detected from the odd-order and even-order signals, respectively. The pulse width is twice that of a serial signal, and the timing of signal acquisition is accordingly twice that of the conventional example, thereby achieving the object described in (1) above.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to the process diagram of FIG. 5 and the timing chart of FIG. 6.

In Figure 6, the same symbols as in Figures 2 and 4 are:
They perform the same operations as those described in FIGS. 2 and 4, respectively. In addition, 22 is a 6-stage shift register, 23
24 is an odd-order synchronization signal pattern detection circuit, 24 is an even-order synchronization signal pattern detection circuit, and 25 is a two-manual AND gate.

Further, the symbols on the left side of FIG. 6 correspond to the symbols marked in FIG. 5, and the timing of the fJ number is shown in the figure.

In FIG. 5, a digital signal modulated by the 4-phase/'SA method is input to the 4-phase P5A input terminal 1,
After being demodulated, it is output in parallel to odd-order and even-order signals. When these signals are passed through the '4u-bus filter 2 and the waveform shaping circuit 5, odd-order and even-order synchronization signals are output in parallel as shown in FIG. 6, 9B and 9C. Next, the respective signals are taken into the shift register 22, and the synchronization signals are detected by the odd-order and even-order synchronization signal pattern detection (b) paths 25 and 24.
A signal of 1" enters the two-manual AND gate 25, and a signal indicating that a synchronous signal of 1 has been detected is output from the synchronous signal detection output terminal.

In this process, consider the timing when odd-order and even-order signals are taken into the shift register. At this time, assuming that the output of the crystal oscillator 5 is the same as the conventional example,
In the conventional example, the minimum pulse widths of 9B and 9C are twice the minimum pulse width T when input to the 6-stage shift register 10 in FIG. 4, so the 16 pulses in FIG. 6A are 2T. It will fall between the width pulses. At this time, the timing at which the signal is taken into the shift register 22 can be taken in the middle of the minimum pulse width of 2T, so if the clock pulse is input into the shift register 8 pulses from the edge, Good. This is output from the output OD of the counter 7 and becomes the timing 8C in FIG.

Here, signals 19 and 4 when detecting a synchronization signal in the conventional example
Comparing the timing of signal 9B when detecting a synchronization signal in the present invention, the minimum pulse width in the conventional example is T and when there are eight 6A pulses, the minimum pulse width in the case of the present invention is 2T and 6A. The number of pulses is doubled to 16,
In addition, the pulse width (minimum) in the conventional example and in the case of the present invention corresponds, so the pulse resolution has double the ability. In the case of the present invention, there is a margin of -T for the advance and 100T for the delay, which is twice as much as the conventional example.

〔Effect of the invention〕

According to the present invention, by detecting the odd-order and even-order synchronization signals from the odd-order and even-order parallel signals after demodulating the 4-phase PSX signal, the time to capture the signal is doubled. Another advantage is that signal detection accuracy is improved, and the margin for delays and advances in time fluctuations is also improved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an example of the shape of a signal when transmitting a digital signal, Fig. 2 is a block diagram showing an example of a circuit for detecting a synchronization signal from a signal having the shape shown in Fig. Figure 3 is a diagram showing the timing of signals in each part shown in Figure 2, Figure 4 is a block diagram showing an example of a conventional circuit that detects a synchronization signal from a signal modulated by 4-phase PSK, and Figure 5 is a diagram showing the timing of signals in each part shown in Figure 2. FIG. 6 is a block diagram showing an embodiment of the present invention, and is a diagram showing the timing of signals of each part shown in FIG. 5. 4... Edge detection circuit, 5... Crystal oscillator, 7...
...Counter, 13...Synchronization signal detection output terminal, 15
...4-phase PSK input terminal, 16... Multiplier, 17.
...Carrier regeneration circuit, 18...Phase shifter, 22...
3-stage shift register, 23... Odd-numbered synchronization signal pattern detection circuit, 24... Even-numbered synchronization signal pattern detection circuit, 25... Two-man power AND gate.

Claims (1)

[Claims] By demodulating the 4-phase PSK signal in a signal reproducing device to the 4-phase P5 signal which is transmitted by dividing the data into 9 blocks and adding a synchronization signal to each block using the 4-phase PSK method. 1. From the obtained odd-order and even-order parallel signals, the odd-order and even-order signal patterns of the synchronization signal are detected separately, and when the signal patterns are detected at the same time, it is determined that the synchronization signal has been detected. 1. A synchronous signal detection circuit comprising a circuit for outputting a signal indicating a signal.