SU1336267A2 - Demodulator of signals with relative phase=shift keying - Google Patents

Abstract

The invention relates to communication technology and increases noise immunity with high noise level. A signal with relative phase shift is received at the input of the former 1 of the paraphase signal. From its output, two paraphase voltages are applied to the 2nd inputs of the comparators (K) 2 and 3. The signals from the inverse outputs K 2 and 3 are used to obtain double frequency. To this end, these signals are logically multiplied in the I-NOT 14. If there are distortions in the double-frequency signal, malfunctions appear. Next, the signal from the output of the 14 14 enters the logical. block 15. At the output of delay block 22, a signal is generated that is delayed by ½ of the input signal period. After logich. signal processing at the output of the OR-NOT 21 signal restores the double-frequency signal, which triggers trigger 6. With trigger 6, two signals of the fundamental frequency are shifted out of phase by 180. At the EL-NE 10-13, a logical . multiplying the signals from the direct outputs K 2 and 3. The result of the multiplication, containing information about the phase of the input signal, is recorded in the triggers 4 and 5. On the ELA 7 and 8 elements, the modulating signal 2 is extracted. 1 tab. ate with-o7 with with C5 Hcc O5 1ChZ

Description

The invention relates to communication technology and is an improvement of the invention according to the author. St. No. 1099411.

The purpose of the invention is to improve the noise immunity with a large level of noise.

FIG. Figure 1 shows the structural electrical circuit of the proposed demodulator; in fig. 2 - timing diagrams for the operation of the logical signal processing unit.

The demodulator contains a shaper 1 paraphase signals, comparators 2 and 3, the first 4, the second 5 and the third 6 triggers, the first 7, the second 8, the third 9, the fourth 10, the fifth 11, the sixth 12, the seventh 13, the eighth 14 elements And- NOT, a logical signal processing unit 15, consisting of the first 16 and second 17 elements NOT, the third 18, first 19, second 20 and fourth 21 OR-NOT, delay block 22.

The demodulator works as follows.

A signal with relative phase shift is received at the input of a paraphase signal generator 1, and from its output two anti-phase voltages are fed to the second inputs of comparators 2 and 3, which form signals suitable for processing them on digital integrated circuits. The trigger threshold of both comparators is set by voltage UQ. The signals from the inverse outputs of the comparators are used to produce double the frequency. For this purpose, signals from the inverted outputs of Comparators 2 and 3 are logically multiplied in the NAND element 14. A double frequency signal is generated at the output of the NAND element 14 only if there is no distortion in the input signal, if there are distortions in the double frequency signal, failures appear . Further, the signal from the output of the NAND 14 element is fed to the logic unit 15. At the output of the delay unit 22, a signal is generated that is delayed by ½ of the input signal period.

Next, the logical processing of signals a II b (Fig. 1) in accordance with the truth table

0

five

FIG. 2 illustrates the operation of the logic unit 15, where a is the signal at the output of the element NOT 16, b is at the output of the element NOT 17, b is at the output of the element OR-NOT 18, g is at the output of the element OR-NOT 19 - at the output of the element OR NOT 20, e - at the output of the element OR NOT 21.

Thus, after logical processing at the output of the element OR-HE 21, the signal of doubled frequency is restored, which triggers trigger 6. Two signals of the main frequency (carrier) are shifted out of phase by 180 ° from the outputs of the trigger. A logical multiplication of signals from the direct outputs of comparators 2 and 3 with the antiphase carrier signals is performed on the elements AND-NE 10-13. The result of the multiplication, containing information about the phase of the input signal, is recorded in the first 4 and second 5 triggers. On the elements AND-NOT 7 and 8 there is a selection of 0 modulating signal. In the NANDEM element 9, the two possible variants of the detection of the modulating signal are combined.

Claims (1)

Invention Formula Demodulator signals relative phase shift keying auth. St. No. 1099411, distinguished by the fact that, in order to increase noise immunity with a high noise level, a logical signal processing unit was inserted, connected between the output of the eighth AND-NES element and the input of the third trigger and consisting of a delay unit, two NOT elements and four elements OR -NO, and the input of the delay unit is connected to the input of the first element NOT and 5 the first inputs of the first and second elements OR-NOT is the input of the logic signal processing unit, the output of the delay unit is connected to the input of the second element NOT, the first input of the third element OR-NOT and the second input of the second element OR NOT, the output of the first element NOT connected to the second input of the third element OR NOT, the output of the second element NOT connected to the second input of the first element OR NOT, the outputs of the first, second and third elements OR NOT connected to the corresponding inputs of the fourth element OR NOT, the output of which is output logic signal processing unit. 0 five but z