JP2870629B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a logic circuit having a function of correcting the timing of both positive and negative phases.

[0002]

2. Description of the Related Art An example of a conventional driving circuit used in a logic LSI is shown in FIG. In this circuit, a drive circuit composed of two cascade-connected inverter circuits is used as a substitute for the input data D and the data in opposite phase ▽ D (▽ is an upper bar meaning inversion).
(The same applies to the following.).

In this circuit, when input data D and data ▽ D of the opposite phase are input to data input terminals 11 and 12, the data signals input to nodes 13 and 14 through inverters 21 and 22 are Signals of opposite phases are output. When this signal further passes through the inverters 25 and 26, a signal having the same phase as the first input data is output to the data output terminals 15 and 16.

As another example of a conventional driving circuit, there is a circuit having a configuration shown in FIG. In this circuit, the clock φ is supplied to the NOR circuits 51 and 5 through the clock input terminal 17.
2 has been entered. That is, in the NOR circuit 51,
The data D and the clock φ are inputted, and the NOR-phase data ΔD and the clock φ are inputted to the NOR circuit 52. In this circuit, a NOR circuit 51 having taken in data D
Is input to the NOR circuit 53 in the next stage. NO
The output signal of the R circuit 53 becomes the output signal Q of this circuit and further becomes the input signal of the NOR circuit 54. The output signal of the NOR circuit 52 that has taken in the negative-phase data #D is input to the NOR circuit 54 in the next stage. The output signal of the NOR circuit 54 becomes the output signal ∇Q of this circuit and further becomes the input signal of the NOR circuit 53.

Next, the operation of the circuit of FIG. 6 will be described with reference to FIG. It is assumed that data D, negative-phase data ΔD, and clock φ are given as shown. At time t1, D is low and ∇D is high, and Q and ∇
Q is also low and high respectively. At time t2, when ∇D goes low, node 14 goes high and ∇Q goes low because clock φ is low.

At time t3, when D goes high,
Node 13 goes low, and accordingly, Q goes high.
At time t4, when clock φ goes high, node 1
Both 3 and 14 are low, but Q and ∇Q remain high and low. At time t5, since the clock φ becomes low, the node 14
Becomes high, but at this time, the output data does not change because ∇Q is already low.

At time t6, when D goes low,
Since clock φ is low, node 13 goes high,
Q goes low. At time t7, when $ D goes high, node 14 goes low, and accordingly $ Q goes high. At time t8, when clock φ goes high, both nodes 13 and 14 go low, but Q, ΔQ
Remains low and high. Hereinafter, the same operation is repeated.

[0008]

In a ratio logic circuit typified by a Si n-MOS circuit or a GaAs DCFL circuit, an enhancement type FET and a diode which constitute a circuit in order to secure an operation margin are provided. Since the value of the current flowing through the precession type FET is designed differently, the rise time and the fall time are different, and the ratio of high to low (duty ratio) of the input signal is the original value (for example, clock signal (Duty ratio = 0.5).

In the driving circuit shown in FIG. 5, the shifted duty ratio cannot be corrected in the above-described case, and the duty ratio is output at the same timing, which causes a malfunction. Further, the circuit shown in FIG. 6 is a latch circuit that is often used when correcting a timing shift or the like, and can correct a timing shift between forward and reverse data under good conditions. The deviation of duty ratio can be corrected. However, in the worst case, as shown in FIG. 7, it is impossible to correct any of the timing deviation of the forward / reverse data and the duty ratio.

The present invention has been made in view of this point, and an object of the present invention is to provide a logic circuit capable of correcting a shift in a duty ratio of a waveform that cannot be corrected by using a latch circuit or the like. This means that malfunction can be prevented even in a high-speed logic LSI.

[0011]

According to the present invention, a first inverter having a first data signal input thereto and an output terminal connected to a first node is provided.
A second data signal having a phase opposite to that of the first data signal and having an output terminal connected to the second node; an input terminal connected to the first node;
A first delay circuit terminal connected to a third node, the input
A terminal is connected to the second node, and an output terminal is connected to the fourth node.
A second delay circuit connected to a point;
A third inverter having an output terminal connected to the first data output terminal, an input terminal connected to the fourth node, and an output terminal connected to the second data output terminal. A fourth inverter, a fifth inverter having an input terminal connected to the first node, and an output terminal connected to the fourth node, an input terminal connected to the second node, and an output terminal And a sixth inverter connected to the third node.

[0012]

In the logic circuit according to the present invention, the influence of one of the positive phase and the negative phase, whichever changes first, is given to the other by the cross-connected inverter circuit, and the other is also changed. This makes it possible to correct the high / low ratio of the input data signal, that is, the duty ratio to 0.5.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first reference example of the present invention. As shown in FIG. 1, the input terminal of the inverter 21 is connected to the data input terminal 11 to which the data D is input, and the input terminal of the inverter 22 is connected to the data input terminal 12 to which the negative-phase data ∇D is input. ing. The output terminal of the inverter 21 is connected to the node 13, and the output terminal of the inverter 22 is connected to the node 14.

The node 13 is further connected to the output terminal of the inverter 23 and the input terminals of the inverters 24 and 25. The node 14 is connected to the output terminal of the inverter 24 and the input terminals of the inverters 23 and 26. The output terminal of the inverter 25 is connected to the data output terminal 15 of the circuit, and the output terminal of the inverter 26 is connected to the data output terminal 16 of the circuit.

Next, the circuit operation of the first embodiment will be described with reference to FIG. It is assumed that data D and $ D are input to the data input terminals 11 and 12, as shown in FIG. At time t1, D is high and ΔD is low. At this time, the output data Q output to the output terminal 15 is high, and the output data Q output to the output terminal 16 is high.
Q is low.

At time t2, when D turns low,
Node 13 is high and Q is low. When the node 13 goes high, the inverter 24 inverts and the node 1
4 goes low, which causes $ Q to go high. At time t3, although ΔD changes to high, the output data D and ΔD do not change because the node 14 is already low.

At time t4, when $ D goes low, node 14 goes high and $ Q goes low. Node 1
When the signal 4 becomes high, the inverter 23 is inverted and the node 13 becomes low, and accordingly, Q becomes high.
At time t5, D changes to high, but since the node 13 is already low, no change occurs in the output data D and ΔD. Hereinafter, the same operation is repeated.

As described above, in this drive circuit, when the data D changes before the negative-phase data .SIGMA.D, the state of the node 13 changes first, and the inverter 24 is changed by the change. Operates to change the state of.
In response to the change in the state of the nodes 13 and 14, the inverters 25 and 26 output data D and .DELTA.D with the same timing.

Conversely, if the data $ D changes before the data D, the state of the node 14 changes first, and the change causes the inverter 23 to operate to change the state of the node 13. . In response to the change in the state of the nodes 13 and 14, the inverters 25 and 26 output data D and .DELTA.D with the same timing. As a result, the deviation of the duty ratio of the input data is corrected.

FIG. 3 is a circuit diagram showing a second reference example of the present invention. In the present reference example, the inverters 21, 22, 25, 26 in the first reference example are connected to the buffer circuits 31, 32, 3
5 and 36.

In this drive circuit, when the data D input to the data input terminal 11 changes before the data $ D input to the data input terminal 12, the state of the node 13 changes first. And the inverter 24
Operate to change the state of the node 14. In response to the change in the state of the nodes 13 and 14, the buffer circuit 3
Data D and .DELTA.D with the same timing are output from 5, 36.

Conversely, when data $ D changes before data D, the state of node 14 changes first, and the change causes inverter 23 to operate to change the state of node 13. . In response to the change in the state of the nodes 13 and 14, the buffer circuits 35 and 36 output data D and ΔD with the same timing. As a result, the deviation of the duty ratio of the input data can be corrected.

FIG. 4 is a circuit diagram showing one embodiment of the present invention. In the figure, parts corresponding to the parts of the first reference example shown in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted. First reference of this embodiment
Differs from the considered example, (node 13a and the node between the input terminal of the output terminal of the inverter 25 in the inverter 21 13
b) between the output terminal of the inverter 22 and the input terminal of the inverter 26 (node 14).
The point is that the delay circuit 42 is connected (between a and the node 14b). The delay time of the delay circuits 41 and 42 is set to be about the delay time of the inverters 23 and 24.

In the first reference example shown in FIG.
If the change occurs earlier than ΔD, the node 14 lags behind the node 13 by the inversion time of the inverter 24, so that the timing of ΔQ is slightly delayed with respect to Q. On the other hand, in the present embodiment, the delay circuit 41 between the inverters,
For example, if D changes earlier than ΔD because 42 is inserted, the potential of the node 13a changes first, and this potential change is transmitted to the nodes 13b and 14b at the same time.
The timings of Q and ∇Q are perfectly aligned.

In the conventional example shown in FIG. 5, there is no function for correcting the timing shift and the duty ratio shift between the outputs, and the circuit using the latch circuit shown in FIG. Now, adjust the timing between outputs,
While the duty ratio could not be corrected, in each of the embodiments of the present invention, by using the cross-connected inverter circuit, the external duty ratio which can make the timing between outputs uniform can be obtained. It can be almost completely corrected.

Further, the embodiment of the present invention is simplified in circuit from the conventional example of FIG. 6 using a two-input NOR circuit,
Further, since a clock signal is not required, a driving circuit for a clock is not required and power consumption does not increase. Therefore, the circuit of the present invention has a circuit configuration advantageous for low power consumption and miniaturization of LSI.

[0027]

As described above, the logic circuit of the present invention is provided between the inverters of two two-stage cascaded inverter circuits.
The delay circuit is inserted into each
Since the output nodes are cross-connected by an inverter, the rising and falling timings of the positive phase and the negative phase can be matched, and the deviation of the duty ratio of the signal can be corrected. Therefore, according to the present invention, it is possible to prevent an erroneous operation of the LSI caused by a shift in the duty ratio, and to contribute to a high-speed operation of the logic LSI.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first reference example of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the first reference example of the present invention.

FIG. 3 is a circuit diagram of a second reference example of the present invention.

FIG. 4 is a circuit diagram of one embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a circuit diagram of another conventional example.

FIG. 7 is a waveform chart for explaining the operation of the conventional example shown in FIG. 6;

[Explanation of symbols]

 11, 12 Data input terminal 13, 13a, 13b, 14, 14a, 14b Node 15, 16 Data output terminal 17 Clock input terminal 21, 22, 23, 24, 25, 26 Inverter 31, 32, 35, 36 Buffer circuit 41 , 42 Delay circuit 51, 52, 53, 54 NOR circuit

Claims (2)

(57) [Claims] A first inverter having an input terminal connected to a first node and an output terminal connected to a first node; a second data signal having an opposite phase to the first data signal; A second inverter having an output terminal connected to the second node, an input terminal connected to the first node, and an output terminal connected to the third node;
A first delay circuit connected to the second node; an input terminal connected to the second node;
A second delay circuit connected to the third node; an input terminal connected to the third node; and an output terminal connected to the first node.
A third inverter connected to the data output terminal of the third node, an input terminal connected to the fourth node, and an output terminal connected to the second node.
A fifth inverter having an input terminal connected to the first node, an output terminal connected to the fourth node, and an input terminal connected to the second node. And a sixth inverter having an output terminal connected to the third node and an output terminal connected to the third node. 2. The logic circuit according to claim 1, wherein the delay times of the first and second delay circuits are substantially the same as the delay times of the fifth and sixth inverters.