JP4097561B2 - Differential clock generation circuit with delay compensation function - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential clock generation circuit with a delay compensation function, and more particularly to a differential clock generation circuit having a waveform shaping function and a function of matching the phase of a differential clock.
[0002]
[Prior art]
An integrated circuit for communication has an input circuit that inputs and latches a high-speed input signal in synchronization with a differential clock. The input circuit with a latch function inputs an input signal while the differential clock is in the first state, generates a state corresponding to the H level or L level of the input signal, and the differential clock is in the second state. When the state is reached, the state is latched and the input signal is cut off. In that case, a differential clock that can sample and latch the input signal from a high-speed input signal is locally generated. Therefore, a differential clock generation circuit for generating a differential clock for synchronization is provided locally.
[0003]
In optical communication using optical fiber, the change of the input signal is very fast, and in order to accurately latch the H level or L level of the input signal, the phase of the differential clock for synchronization may be matched. Desired. The phase difference between the normal clock and the inverted clock of the differential clock means that the timing of the rising edge of the normal clock and the falling edge of the inverted clock match, and the falling edge of the normal clock and the rising edge of the inverted clock. Are exactly the same, and exactly, both clocks have a phase difference of exactly 180 °. Therefore, the differential clock generation circuit is required to have a function of compensating for the delay of the edges of both clocks.
[0004]
FIG. 1 is a diagram showing a conventional differential clock generation circuit with a delay compensation function and a waveform diagram. Differential clocks CLK and CLKx having the same phase are generated from the normal input Vin and the inverted input Vinx generated by a voltage controlled oscillation circuit (VCO) (not shown). Inverters A11, A21, and A31 are connected in cascade on the forward input Vin side, and inverters A12, A22, and A32 are connected in cascade on the inverted input Vinx side. For delay compensation at the input and output terminals of each inverter Inverters B11, B12, B21, B22, B31, and B32 are provided. These inverters are CMOS inverters composed of P-channel transistors and N-channel transistors. The waveform diagram shows the outputs Vout and Voutx of the inverters A11 and A12 for both inputs Vin and Vinx. This conventional differential clock generation circuit is described in the following document.
[0005]
[Patent Literature]
The operation of the inverters A11 and A12 will be described. When the input voltage Vin rises, when the P-channel transistor of the inverter A11 is turned off, the output voltage Vout starts to fall, and the input voltage Vinx Falls, the output voltage Voutx starts to rise when it reaches a level that turns off the N-channel transistor of the inverter A12. If the phase of the normal output Vout is ahead of the phase of the reverse output Voutx, the inverter B21 forcibly raises the reverse output Voutx to advance the phase of the reverse output Voutx. To do. Conversely, when the phase of the forward rotation side output Vout is delayed from the phase of the reverse rotation side output Voutx, the forward rotation side output Vout is forcibly raised by the inverter B22 to advance the phase of the forward rotation side output Vout. Try to. As a result, the phases of the normal rotation clock CLK and the inversion clock CLKx come to coincide. That is, this differential clock generation circuit has a function of compensating for the delay between both clocks CLK and CLKx.
[0006]
[Problems to be solved by the invention]
However, in the differential clock generation circuit of FIG. 1, since the output of the inverter A11 is connected to the inputs of the inverters A21 and B21, the fanout of the inverter A11 becomes 2, and the rise time tr (time of the output of the inverter A11) of rising) and falling time tf (time of falling) become longer, the rising and falling waveforms of the differential clock become slow, and a differential clock having sharp rising and falling edges can be generated. It has a problem that it cannot be done. In other words, by providing the inverters B11, B12, B21, B22, B31, B32, the delay of the edge of one clock is compensated, but the inverters A11, A21, A31, A12, A22 that propagate the clock by that inverter , The fanout of A32 increases and the slope of the edge becomes large.
[0007]
Accordingly, an object of the present invention is to provide a differential clock generation circuit capable of solving the above-described problems and shortening the rise time and the fall time to compensate for the mutual delay.
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, in a differential clock generation circuit that propagates a normal clock and an inverted clock to compensate for a phase shift between both clocks, a plurality of normal clocks that propagate the normal clock and are connected in cascade are provided. Side CMOS inverter and an inversion side CMOS inverter that propagates the inversion clock and is connected in series, and the normal side inversion CMOS inverter and the inversion side CMOS inverter are connected between the first power source and the output terminal. A first inductance provided in series with the channel transistor, and a second inductance provided in series with the N-channel transistor between the second power supply and the output terminal, and between the first inductance and It has a mutual inductance between the second inductances.
[0009]
According to the first aspect, the phase of the clock that is delayed in phase is further accelerated by the induced current caused by the mutual inductance between the first inductance and the second inductance. Thus, the operation is performed so that the rising and falling edges of both clocks become steep. Therefore, the differential clock generation circuit can generate a differential clock in which the phases of the rising edge and the falling edge coincide.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. However, the protection scope of the present invention is not limited to the following embodiments, but extends to the invention described in the claims and equivalents thereof.
[0011]
FIG. 2 is a diagram illustrating a differential clock generation circuit according to the present embodiment. A normal rotation input Vin generated by a voltage controlled oscillation circuit (VCO) (not shown) is input to the inverter A11 and propagates through a plurality of cascade-connected normal inverters A11, A21, A31 to generate a normal rotation clock CLK. Generated. Similarly, an inverting input Vinx generated by a VCO or the like (not shown) is input to the inverter A12 and propagates through a plurality of inverting side inverters A12, A22, A32 connected in cascade to generate an inverted clock CLKx. Each inverter has a first inductance Lp, Lpx between the output terminal and the first power supply Vcc, and a second inductance Ln, Lnx between the output terminal and the second power supply (ground) Vss, respectively. Provided. The first inductance and the second inductance have mutual inductances Mp and Mn, respectively. When a current is generated in one inductance, an induced back electromotive force is generated in the other inductance.
[0012]
FIG. 3 shows a CMOS inverter circuit. FIG. 3 shows the inverter A11 of FIG. 2 and the first and second inductances Lp and Ln connected thereto. In the example of FIG. 3A, a first inductance Lp is provided between the power supply Vcc and the P-channel transistor pMOS, and a second inductance Ln is provided between the ground Vss and the N-channel transistor nMOS. . In the example of FIG. 3B, a first inductance Lp2 is provided between the P-channel transistor pMOS and the output Vout, and a second inductance Ln2 is provided between the N-channel transistor nMOS and the output Vout. ing. In either example, a first inductance is provided in series with the P-channel transistor pMOS between the power supply Vcc and the output Vout, and a second inductance is provided in series with the N-channel transistor nMOS between the ground Vss and the output Vout. Is provided.
[0013]
In the operation of the CMOS inverter shown in FIG. 3, when the input Vin rises from the L level to the H level, the N channel transistor nMOS becomes conductive when the input voltage exceeds the threshold voltage of the N channel transistor nMOS from the ground Vss level, and the output Vout A current In is generated that discharges the parasitic capacitance. However, a current Ip from the power supply Vcc to the ground Vss is also generated in the P channel transistor pMOS which is in a conductive state at that time, and as a result, a through current is temporarily generated. Accordingly, in this state, the output Vout level has not yet started to decrease. When the input Vin further rises and exceeds the level lower than the threshold voltage of the P-channel transistor pMOS than the power supply Vcc, the P-channel transistor pMOS becomes non-conductive, and the level of the output Vout is lowered to the ground Vss level due to the current In.
[0014]
In other words, when the input Vin rises, the current Ip accompanying the generation of the through current is temporarily generated in the first inductance Lp, and the current Ip is no longer present in the second inductance Ln after the current Ip has disappeared since the generation of the through current. When In continues and the output Vout drops to the ground level Vss, the current In disappears. On the contrary, when the input Vin falls, the current In accompanying the generation of the through current is temporarily generated in the second inductance Ln, and after the current In has been lost in the first inductance Lp since the generation of the through current. However, when the current Ip continues and the output Vout rises to the power supply level Vcc, the current Ip disappears.
[0015]
The operation of the differential clock generation circuit of FIG. 2 will be described below in consideration of currents generated in the first and second inductances of the inverter.
[0016]
FIG. 4 is an operation waveform diagram of the CMOS inverters A11 and A12 when the edges of the normal input and the inverted input are in phase. The solid line is a waveform diagram on the forward rotation side, and the broken line is a waveform diagram on the reverse side. As shown in (1), at the same timing, the normal input Vin rises and the inverted input Vinx falls. In response to the input, the inversion operation of the inverters A11 and A12 causes the normal output voltage Vout to fall and the inversion output voltage Voutx to rise.
[0017]
As described in the operation of the CMOS inverter in FIG. 3, in response to the rising edge of the normal input Vin, a current In ((3) in the figure) is generated in the N-channel transistor nMOS of the inverter A11, and the P of the inverter A11 is further increased. A temporary through current Ip ((6) in the figure) is generated in the channel transistor pMOS. The current In of the N-channel transistor nMOS also flows through the second inductance Ln, and a negative current Inkx ((5) in the figure) is generated in the second inductance Lnx of the inverter A12 due to the induced back electromotive force due to the mutual inductance Mn. To do. However, the current Inkx is generated only during the through current generation period in which the current Ipx ((6) in the figure) and the current Inx ((3) in the figure) simultaneously flow in the inverter A12 on the inverting side. After the time t1, the N-channel transistor nMOS of the inverter A12 is turned off, so that no current due to the induced back electromotive force is generated in the second inductance Lnx. On the other hand, the current Ip ((6) in the figure) temporarily generated in the P-channel transistor pMOS of the inverter A11 also flows through the first inductance Lp, and the first counter current of the inverter A12 is generated by the induced back electromotive force due to the mutual inductance Mp. A negative current and a positive current Ipkx ((8) in the figure) are generated in the inductance Lpx.
[0018]
In short, due to the operation of the inverter A11 on the forward rotation side, the negative inductance and the positive current Ipkx ((8) in the figure) are included in the first inductance Lpx and the second inductance for the inverter A12 on the reverse rotation side. Since a negative current Inkx ((5) in the figure) is generated in Lnx, the current flowing from the output Voutx of the inverter A12 to the ground Vss is reduced by the negative current Inkx, and the rising of the inverting side output Voutx is accelerated. That is, the rising waveform becomes steeper.
[0019]
On the other hand, when the mutual induction action to the normal rotation side inverter A11 by the operation of the inversion side inverter A12 is described, it is completely opposite to the above description. That is, in response to the fall of the inverting input Vinx, in the inverting-side inverter A12, a current Inx is temporarily generated in the transistor nMOS, and a large driving current Ipx flows in the transistor pMOS. A negative current and a positive current Ink ((4) in the figure) are generated in the second inductance of the forward inverter A11 induced by the current Inx, and the first inductance of the inverter A11 is induced by the current Ipx. A negative current Ipk ((7) in the figure) is generated. As a result, the falling of the normal output Vout is accelerated, and the falling waveform becomes steeper.
[0020]
As described above, due to the mutual inductive action due to the mutual inductance, the respective output drive currents increase, and the rising and falling waveforms of the forward rotation clock and the inverted clock become steep. That is, the differential clock generation circuit of FIG. 2 has a waveform shaping function.
[0021]
FIG. 5 is an operation waveform diagram of the CMOS inverters A11 and A12 when the phase of the edge of the normal input is ahead of the phase of the edge of the inverted input. In the example of FIG. 5, for the inverters A11 and A12, operation waveforms when the rising edge of the normal input Vin occurs at a timing earlier than the falling edge of the inverted input Vinx are shown.
[0022]
A current Inx ((3) in the figure) and a current Ip ((6) in the figure) generated in the inverter A11 with the rising timing of the normal input Vin being early are the current Inx (in the figure (6)) in the inverter A12. It occurs at a timing earlier than the middle (3)) and the current Ipx ((6) in the figure). In FIG. 4, it can be understood that the timing is earlier than that in which the generation timings of these currents coincide.
[0023]
Therefore, the effect of the inductance of the forward inverter A11 on the inverting inverter A12 based on the induced counter electromotive force due to the currents In and Ip will be described. The current In ((3) in the figure) of the transistor nMOS of the inverter A11 is the second. The negative inductance Inkx ((5) in the figure) is generated in the second inductance Lnx of the inverting-side inverter A12 due to the mutual inductance Mn. However, this period of the negative current Inkx is shorter than that in the case of FIG. That is, while the N-channel transistor nMOS of the inverting inverter A12 is conducting and the current Inx flows (t3), the current In flowing through the N-channel transistor nMOS of the non-inverting inverter A11 is changing ( During the rise of t2, a negative current Inkx is generated. As the timing shifts, the rise of the current In is completed while the current Inx is being generated, so the period of the negative current Inkx is shortened. However, the rising operation of the inversion side output Voutx is accelerated by the negative current Inkx.
[0024]
On the other hand, when a current Ip ((6) in the figure) of the transistor pMOS of the normal inverter A11 is generated in the first inductance Lp, a positive current Ipkx (in the figure) is generated in the first inductance Lpx of the inverter A12. (8)) occurs. This current Ipkx is during the period (t5) during which the P-channel transistor pMOS of the inverting inverter A12 conducts and the current Ipx flows (t5), and the current Ip flowing through the P-channel transistor pMOS of the normal rotation A11 changes. This is a positive current generated during the period (t4) and corresponding to the decrease in the current Ip. As compared with FIG. 4 (8), as hatched, the period t5 in which the current Ipx is generated is shifted, so that a negative current corresponding to the rising operation of the current Ip is not generated. That is, the rising operation of the inversion side output Voutx is accelerated by the current Ipkx.
[0025]
As described above, the rising operation of the output Voutx of the inverting inverter A12 is accelerated by the current Inkx and Ipkx ((5) (8) in the figure) due to the influence of the operation of the normal inverter A11.
[0026]
Conversely, the effect of the operation of the inverting inverter A12 on the forward inverter A11 will be described. A current Inx ((3) in the figure) is generated in the second inductance Lnx of the inverting inverter A12, and the current Inx During the period t3 during which the current is generated, the current In is generated in the transistor nMOS of the normal inverter A11 (t2). Therefore, a negative current and a positive current Ink ((4) in the figure) are generated in the second inductance Ln of the forward inverter A11 by the induced counter electromotive force with respect to the current Inx. Since this current Ink is a negative current and a positive current, there is no acceleration to the falling operation of the normal output Vout.
[0027]
On the other hand, a current Ipx ((6) in the figure) is generated in the first inductance Lpx of the inverting-side inverter A12, and the first inductance Lp of the normal-rotation-side inverter A11 is negative due to the induced back electromotive force generated by the current Ipx. A current Ipk ((7) in the figure) is generated. Since the current Ipx is generated only during the period t4 in which the transistor nMOS of the normal rotation side inverter A11 is conducting, the generation period of the negative current Ipk is shorter than that in FIG. 4 (7). Due to this negative current Ipk, the falling operation of the normal output Vout is accelerated.
[0028]
As described above, due to the influence of the operation of the inverting inverter A12, the falling operation of the output Vout of the normal inverter A11 is accelerated only by the current Ipk ((7) in the figure). Therefore, from the relationship of Ipk <Inkx + Ipkx, acceleration to the inversion side output Voutx is larger than acceleration to the normal side output Vout. As a result, in total, the rising operation of the inverting output Voutx is accelerated more strongly than the falling operation of the non-inverting output Vout, and the reversal of the one with the phase delay while both clock edges become steep The clock edge becomes steeper and the delay is compensated.
[0029]
FIG. 6 is an operation waveform diagram of the CMOS inverters A11 and A12 when the phase of the edge of the normal input is ahead of the phase of the edge of the inverted input. In the example of FIG. 6, for the inverters A11 and A12, operation waveforms when the falling edge of the normal rotation input Vin occurs at an earlier timing than the rising edge of the inverting input Vinx are shown. The waveform of FIG. 6 is merely the reverse of the P channel side and the N channel side of the waveform of FIG. Therefore, also in the case of FIG. 6, the falling of the inverting side output Voutx is accelerated by the currents Inkx and Ipkx, and the rising of the normal side output Vout due to the current Ipk is accelerated. The inversion side output Voutx acceleration is greater than the forward rotation side output Vout acceleration.
[0030]
As described above, according to the differential clock generation circuit of FIG. 2, the rising and falling of both clocks are accelerated by the generation of the induced counter electromotive force current due to the mutual inductance between the forward inverter and the inverting inverter, The rise and fall of the clock that is delayed in phase is accelerated more strongly. Therefore, this differential clock generation circuit has both a waveform shaping function and a delay compensation function.
[0031]
FIG. 7 is a diagram illustrating an operation simulation result of the differential clock generation circuit of FIG. (1) indicates a normal rotation input and an inverting input, and the solid line is more advanced in phase than the broken line. (2) shows normal output and reverse output after passing through a 5-stage inverter, and as is clear from the fact that the point where both waveforms cross is close to the center, the phase difference between the two is reduced. ing. Further, (3) shows the output waveform after passing through the 10-stage inverter, and (4) shows the output waveform after passing through the 15-stage inverter. It is clear that the phase difference between both waveforms is reduced by increasing the number of inverter stages.
[0032]
In the differential clock generation circuit of FIG. 2, all inverters are provided with inductance, but some inverters may be provided with inductance.
[0033]
The above embodiment is summarized as follows.
[0034]
(Supplementary Note 1) In a differential clock generation circuit that propagates a forward clock and an inverted clock to compensate for a phase shift between both clocks,
One or more forward CMOS inverters propagating the forward clock and connected in series;
One or more inversion-side CMOS inverters that propagate the inversion clock and are connected in series;
The forward-side CMOS inverter and the inversion-side CMOS inverter are provided between a first inductance provided in series with a P-channel transistor between a first power supply and an output terminal, and between a second power supply and the output terminal. A differential clock generation circuit having a second inductance provided in series with an N-channel transistor and having a mutual inductance between the first inductance and the second inductance.
[0035]
(Appendix 2) In Appendix 1,
The differential clock generation circuit, wherein the first inductance is provided between a source of the P-channel transistor and a first power supply.
[0036]
(Appendix 3) In Appendix 1,
The differential clock generation circuit, wherein the second inductance is provided between a source of the N-channel transistor and a second power supply.
[0037]
(Appendix 4) In Appendix 1,
The differential clock generation circuit, wherein the first inductance is provided between a drain of the P-channel transistor and an output terminal.
[0038]
(Appendix 5) In Appendix 1,
The differential clock generation circuit, wherein the second inductance is provided between a drain and an output terminal of the N-channel transistor.
[0039]
(Appendix 6) In Appendix 1,
A differential clock generation circuit, wherein rising and falling edges of the normal clock are aligned with falling and rising edges of the inverted clock.
[0040]
(Appendix 7) In Appendix 1,
A normal clock generated by passing through the plurality of forward-side CMOS inverters and an inverted clock generated by passing through the plurality of reverse-side CMOS inverters are used for input latches of the input circuit of the communication integrated circuit. A differential clock generation circuit characterized by being output as a clock.
[0041]
【The invention's effect】
According to the present invention, it is possible to provide a differential clock generation circuit that can compensate for the delay of the differential clock and can further sharpen the waveform. This differential clock generation circuit can be used as a circuit for generating a local clock of a communication IC.
[Brief description of the drawings]
FIG. 1 is a diagram showing a conventional differential clock generation circuit with a delay compensation function and a waveform diagram.
FIG. 2 is a diagram showing a differential clock generation circuit in the present embodiment.
FIG. 3 is a diagram showing a CMOS inverter circuit.
FIG. 4 is an operation waveform diagram of the CMOS inverters A11 and A12 when the phases of the edges of the normal input and the inverted input are the same.
FIG. 5 is an operation waveform diagram of the CMOS inverters A11 and A12 when the phase of the edge of the normal input is ahead of the phase of the edge of the inverted input.
FIG. 6 is an operation waveform diagram of the CMOS inverters A11 and A12 when the phase of the edge of the normal input is ahead of the phase of the edge of the inverted input.
7 is a diagram illustrating an operation simulation result of the differential clock generation circuit of FIG. 2;
[Explanation of symbols]
A11, A21, A31: Forward rotation side CMOS inverter,
A12, A22, A32: CMOS inverter on the inverting side,
Lp, Lpx: first inductance,
Lu, Lux: second inductance

Claims (5)

In the differential clock generation circuit that propagates the forward clock and the inverted clock,
A forward-side CMOS inverter that propagates the forward clock;
An inversion-side CMOS inverter that propagates the inversion clock;
The forward rotation side CMOS inverter includes a first inductance provided in series with a first P-channel transistor between a first power source and a first output terminal, a second power source, and the first output. And a second inductance provided in series with the first N-channel transistor between the terminals,
The inverting-side CMOS inverter includes a third inductance provided in series with a second P-channel transistor between the first power supply and the second output terminal, a second power supply, and the second output. And a fourth inductance provided in series with the second N-channel transistor between the terminals and
Differential clock generation circuit characterized by having a respective mutual inductances between and between the second inductance and the fourth inductance of the third inductance and said first inductance. In claim 1,
It said first and third inductance differential clock generation circuit, characterized in that provided respectively between the source and the first power supply of the first and second P-channel transistor. In claim 1,
The second and fourth inductance differential clock generation circuit, characterized in that provided respectively between the source and the second power supply of the first and second N-channel transistor. In claim 1,
A differential clock generation circuit, wherein rising and falling edges of the normal clock are aligned with falling and rising edges of the inverted clock. In claim 1,
A normal clock generated by passing through the forward CMOS inverter and an inverted clock generated by passing through the inverted CMOS inverter are output as input latch clocks for the input circuit of the communication integrated circuit. A differential clock generation circuit.

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