JPH0242814A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain complementary double-phase signal to accompany same time delay in both output sides by connecting two inverters across between the output side of an even number of inverters and the output side of an odd number of inverters. CONSTITUTION:After a node N11 goes to be L, a node N14 tries to be L H after a delay time tau24 of an inverter 24, however, it can be H by the influence of an inverter 26. On the other hand, after the node N11 goes to be L, a node N13 tries to be H L after delay times tau22+tau23 of inverters 22 and 23. At such a time, since N14 tries to be L H preceding to the N13, the output of an inverter 25 next tries to be H L. Thus, the N13 tries to be L earlier than the delay times tau22+tau23 and the operation of the N13 is transmitted to the inverter 26. Then, the output of the inverter 26 goes to be H. Thus, the N14 rapidly goes to be H. Accordingly, in the N13 and 14, the complementary signals of double phases to have the same timing of a signal change appear.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated circuit for obtaining complementary two-phase output signals from a single-phase input signal, and particularly to a circuit driven by two-phase signals. The present invention relates to a semiconductor integrated circuit that serves as a signal source.

(Prior art) Conventionally, as a technology in this field,
There was one described in Publication No. 63829. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional semiconductor integrated circuit.

This semiconductor integrated circuit includes an input terminal 1 for an input signal D1,
It is provided with an output terminal 2 for the output signal Q1, an output terminal 3 for the reverse phase output signal 1, and inverters 4 to 6. An output terminal 2 is connected to the input terminal 1 via an inverter 4, a node N1, and an inverter 5, and an output terminal 3 is also connected via an inverter 6.

FIG. 3 is a time chart showing the operation of FIG. 2,
The operation of the semiconductor integrated circuit shown in FIG. 2 will be explained with reference to this figure. However, inverters 4.5° and 6 each have τ1. It is assumed that approximately the same delay times of τ2° and τ3 are required.

First, the initial state is "low level" (hereinafter referred to as "L").

) is applied to the node Nl.

Output signal Ql, negative phase negative phase output signal furnace each at high level (
(hereinafter referred to as II HII), “1.II, II
Assume that it is HI+.

At time T, when the input data D1 changes from "1, 11" to "H", the output side node N1 of the inverter 6 changes from "H" to +
1 L becomes 11. At this time, a delay of time τ1 corresponding to the delay time of the inverter 6 occurs with respect to time T. Similarly, the reverse phase output signal 1 is delayed by the delay time τ3 of the inverter 8 with respect to time T1, and is changed from 11 HII to L I
Become I. Furthermore, the output signal Q1 changes from "L" to "H'" after a delay of τ2 of the inverter 7 with respect to the time when the node N1 changes from Hu to °L'°, that is, after a time τ1 delay from time T1. It's going to change.

In this way, this semiconductor integrated circuit outputs the output signal Q1 that is in phase with the input signal D1 input to the input terminal 1 by (τ1+τ2
) is sent out from the output terminal 2 with a time delay of .tau.3, and an opposite phase output signal D1 having the opposite phase to the input signal D1 is sent out from the output terminal 3 with a time delay of .tau.3.

(Problems to be Solved by the Invention) However, the semiconductor integrated circuit having the above configuration has the following problems.

This type of circuit that obtains complementary two-phase output signals from a single-phase input signal is used in various circuits such as flip-flop circuits. In order for such a circuit to operate stably and at high speed without causing malfunctions, it is desirable that the time difference between the output signal Q1 and the opposite phase output signal 1 be as small as possible.

However, in the semiconductor integrated circuit having the above configuration, as is clear from FIG.
Since both delay paths are different, it is not possible to invert the phase at the same timing in response to a change in the logic of the input signal D1.

Specifically, the output signal Q1 performs a signal inversion operation with a delay of (τ1+τ2−τ3) with respect to the opposite phase output signal 1. As described above, in conventional semiconductor integrated circuits, it is difficult to obtain signals of both phases having a highly accurate complementary relationship.

The present invention provides a semiconductor integrated circuit that solves the problem of the prior art, which is that it is difficult to obtain complementary two-phase output signals at the same time timing from a single-phase input terminal. It is something to do.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an even number of inverters that sequentially invert input signals and output output signals; In a semiconductor integrated circuit comprising an odd number of inverters that output phase-inverted output signals, two inverters are interposed between the output side of the even number of inverters and the output side of the odd number of inverters. It was designed to connect.

(Function) According to the present invention, since the semiconductor integrated circuit is configured as described above, the two inverters cross-connected between the output side of the even numbered inverters and the output side of the odd numbered inverters are as follows: In the output side paths of even-numbered inverters and the output-side paths of odd-numbered inverters, the delay time is shortened in the path with a long delay time required for signal inversion operation, and the delay time is extended in the path with a short delay time. It works to match the delay times of both.

Therefore, in response to changes in the input signal, a complementary output signal and an opposite phase output signal are output at the same timing. Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a circuit diagram of a semiconductor integrated circuit showing an embodiment of the present invention.

This semiconductor integrated circuit has an input terminal 11 for input signal D2.
, an output terminal 12 for the output signal Q2, an output terminal 13 for the opposite phase output signal 2 which is opposite in phase to the output signal Q2, and a MOS-
FET' (insulated gate field effect transistor) and ME
It includes inverters 21 to 28 formed of S-FETs (Schottky barrier gate field effect transistors) and the like.

The input terminal 11 is connected to the input side of an inverter 21, and an inverter 22, a node N12, and an inverter 23 are connected to an output side node NIL of the inverter 21, and an inverter 24 is also connected. Inverters 25 and 26 are sash-connected between the output node N13 of the inverter 23 and the output node N14 of the inverter 24. Furthermore, nodes N13 and N14
are connected to output terminals 12 and 13 via buffer inverters 27 and 28, respectively.

FIG. 4 is a time chart showing the operation of FIG. 1, and the operation of the semiconductor integrated circuit of FIG. 1 will be explained with reference to this diagram.

It is assumed that the inverters 21 to 28 each require approximately the same delay time when inverting and outputting the signals input into the inverters.

First, as an initial state, input data D2 of +1111
is applied, and note Ni1. Suppose that N13, the opposite phase output signal 2 is fl HII, the nodes N12 to N14, and the output signal Q2 are "L".

Next, at time T, the input signal D2 changes from 'L'° to II
When the signal becomes HII, the node N11 becomes "L" after a delay time τ21 of the inverter 21. After the node Nil changes to 'L'° and further passes through the delay time τ22 of the inverter 22, that is, with respect to time T, the node N12 becomes (τ21+
τ22) becomes 11 HII with a delay. At this time, node N
The signal (logic) of il and the signal of node N12 are mutually inverted and complementary signals of both phases, but in terms of timing, there is a time delay of 22, which is the same as in the conventional circuit.

Here, the temporal correlation of changes in nodes N13 and N14 in response to changes in input signal D2 will be considered.

For example, node N13. In a state where there are no inverters 25 and 26 connected across N14, the delay time τ23 of the inverter 23 and the delay time τ2 of the inverter 24 are
4 are the same.

In this case, the change in the signal at node N13 is the change in the signal at node N13.
A delay corresponding to the delay time τ22 of the inverter 22 always occurs with respect to a change in the signal at the inverter 22.

Due to this delay, node N13. Inverters 25 and 26 connected across N14 play the following roles.

First, after the node Nil becomes "L", the node NL4 changes from the voltage "L" through the delay time τ24 of the inverter 24.
Although the signal attempts to become "H", it is affected by the output of "Lll" in the inverter 26 at this point. Therefore,
The node N14 cannot become ``H'' immediately even after the delay time τ24 of the inverter 24 has elapsed.

On the other hand, after node Nil becomes L, node N13
After the delay time (τ22+τ23) of the inverters 22 and 23, it is about to go from "'H'° to "L". At this time, the signal at the node N14 changes before the node N13, and the signal changes from II L II to " Since the output of the inverter 25 is about to become high, the output of the inverter 25 becomes high.
” to “L”. Therefore, node N13
is the inverter 22 with the help of the output of the inverter 25.
．． It attempts to go to "L" much faster than the delay time (τ22+τ23) of 23 times. Furthermore, such a node N13
Due to the function of
6, the output of the inverter 26 becomes high, so that the node N14 quickly attempts to become high with the help of the output of the inverter 26.

In this way, two complementary phase signals appear at nodes N13 and N14 with the same signal change timing. Therefore, if the buffer inverters 27 and 28 are configured with equal delay times, the inverters 27 and 28 can be configured with equal delay times.
From the output terminals 22 and 23 via 28, an output signal Q2 and an opposite phase output signal Q2, which have the same signal change timing and are complementary signals, are obtained.

The above explanation was about the case where the input signal D2 goes from "L" to 11811, but the same applies to the case where the input signal D2 goes from "H" to "L".

This embodiment has the following advantages.

When the signal voltage of input signal D2 changes, node N1B,
Inverters 25 and 26 cross-connected between nodes N13 and N14 transfer the signal they held before the input signal D2 changed to nodes N13. Alternatively, it is transmitted to node N14.

These signals shorten the delay time on the side of node N13 with a long delay path, and conversely shorten the delay time on the side of node N14 with a short delay path.
The side has an adjustment function that extends the delay time. Therefore, it is possible to obtain complementary two-phase signals with the same time delay in accordance with changes in the signal voltage of the input signal D2.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

■ If the configuration is omitted from the inverter 21 in Fig. 1,
The output signal Q2 and the opposite phase output signal Q2 can have polarities opposite to those of the above embodiment.

■ In the above embodiment, the first delay path from node Nil to node NIB is connected to two inverters 22.2B, and the second delay path from node Nil to node N14 is connected to one inverter.
However, the first delay path may be configured with an even number of four or more inverters, and the second delay path may be configured with an odd number of three or more inverters.

(Effects of the Invention) As described above in detail, according to the present invention, two inverters are cross-connected between the output side of an even number of inverters and the output side of an odd number of inverters. Therefore, complementary two-phase signals with the same time delay can be obtained at the output side of even-numbered inverters and the output side of odd-numbered inverters. It is possible to obtain a complementary output signal and an opposite phase output signal at the timing of .

Therefore, it can be expected to be an extremely useful circuit that can be used as a signal source for a circuit driven by complementary two-phase signals.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a semiconductor integrated circuit showing an embodiment of the present invention, Fig. 2 is a circuit diagram of a conventional semiconductor integrated circuit, Fig. 3 is a time chart of Fig. 2, and Fig. 4 is a circuit diagram of a conventional semiconductor integrated circuit. This is a time chart. 21-28... Inverter, D2...
Input signal, Q2... Output signal, mutual 2...
・Reverse phase output signal.

Claims (1)

[Claims] An even number of inverters that sequentially invert an input signal and output an output signal, and an odd number of inverters that invert the input signal and output an opposite phase output signal that is opposite in phase to the output signal. A semiconductor integrated circuit comprising: two inverters cross-connected between the output side of the even number of inverters and the output side of the odd number of inverters.