SU1376260A1 - Apparatus for receiving relative bipulse signal - Google Patents

Abstract

The invention relates to telecommunications technology and can be used in digital transmission systems. The purpose of the invention is to increase the reliability of reception with a high level of interference. The device contains an input matching block 1, y-2, junction lock 3, one-shot 5 with restart, register 6, K3-trigger;, 8, single-vibrator 10, element 11, shaper 12 clock signal, D- trigger 14. The goal is achieved by introducing into the device of the front 9 cutoff, the clock phasing block of logic block 7 and the crystal oscillator 4. 2 Il.

Description

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The invention relates to telecommunications engineering and can be used in three-way transmission systems.

The purpose of the invention is to increase the reliability of reception with a high level of interference.

FIG. 1 shows the electrical circuit of the proposed device; in fig. 2 - EP1FY stresses, which determine its work.

A device for receiving a relative bi of a signal contains an input matching unit 1, an amplifier 2, a latch of 3 transitions, a quartz auto-oscillator 4, a one-shot 5 with restarting, a register 6, a logic block 7, an RS flip-flop 8, a front 9 selector, a one-shot 10 , element 11, shaper signal generator 12, clock phasing unit 13, and D-flip-flop 14.

The device works as follows.

The relative bi-pulse signal (Fig. 1) passed through the connecting line enters the input matching unit 1, which is designed to make the transition from the symmetrical connecting line (in the case that the connecting line is not coaxial) to the unbalanced input of the amplifier -2 to match the input of the amplifier 2 with characteristic impedance of the connecting line. Amplifier 2 amplifies the signal arriving at its input from the output of input matching unit 1 to a value that ensures the operation of latch 3 transitions, which converts the signal arriving at its input (FIG. 26 and corresponding to the original two-position signal (FIG. 2a), into a sequence of short 1-spools, the temporary positions of which correspond to the temporary positions of the transitions relative to the bi-pulse signal (Fig. 2c). The quartz oscillator 4 produces a clock signal ensuring the operation of the register 6. The single-oscillator 5c repeats by a wide triggering, it expands the pulses arriving at its input to a value equal to: 0.75 T, where T is the clock interval of the information signal. The distinctive feature of the signal at the output of the one-oscillator 5 with restarting (Fig. 2d) is that on those clock intervals, where in

t

ten

15 20

25 30 - Q

0

 A bi-pulse signal has two or more transitions, its significant state is unchanged, and where one transition changes.

Register 6, the input of which receives a signal from the output of the one-shot 5 with restarting, and logic block 7, whose inputs are connected to the direct outputs of the trigger cells of the register 6, analyze the signal (Fig. 2d) and generate two signals (Fig. 2e). ), the first of which is fed to the R input, and the second to the S input of the RS flip-flop 8. From the output of the last signal (Fig. 2g) goes to the D input of the B flip-flop 14, to the C input of which a clock signal is applied from the output of the clock phasing unit 13. In the clock signal generator 12, a signal whose frequency is equal to twice the frequency of the clock signal is first formed from the relative bi-pulse signal transitions, and then by dividing the frequency, a clock signal is generated whose phase is uncertain (may differ by 180) (Fig. 2 l and m). To use this signal as a clock, it is necessary to ensure the certainty of its phase. For this purpose, in the clock phasing unit 3, this signal is compared with the reference signal and, according to the results of the comparison, its direct or inverse form is taken as the clock signal. By means of clock generator elements 12, affecting the phase shift of the clock signal, this phase is set so that the signal transitions (Fig. 2g) in the temporal position coincide approximately with the middle distance between the clock signal transitions (Fig. 2 and m) .

The reference signal is formed at the output of the And 11 element (Fig. 2k) in the presence of zeros in the signal. Prior to the appearance of zeros in the signal (when receiving continuous units), the phase of the clock signal does not affect the quality of decoding.

The front selector 9 from each / transition from high level to zero in the signal arriving at its input from the output of the one-shot one-shot 5, re-starting, generates short pulses (Fig. 2h), which after spreading in the one-shot 10 to a value of 0.5 T

arrive at the first input element And 11 (Fig. 2i), at the second input of the latter receives pulses from the release of the latch 3 transitions. In block 13 of clock clock phasing, the reference signal (Fig. 2k) is compared with the direct and inverse waveforms from the output of clock generator 12, and the signal corresponding to fig. 2l, which from the output of the clock phasing unit 13 is fed to the synchronous input of the D-flip-flop 14 and to the output of the clock signal of the device. Until the clock signal is phased (before the first zero appears in the signal), the phase of the clock signal may differ by 180, i.e. At the output of the clock signal clock unit 13, the signal may correspond to FIG. 2l or fig. 2m When receiving continuous units, the phase of the clock signal does not affect the quality of the signal being decoded, but from the moment the transitions appear in the decoded signal (Fig. 2g), the clock signal must be phased, since the phase positions of the transitions will depend on the phase of the clock signal.

Since the clock signal is phased at the moment when the first pulse appears at the output of the And 11 element (Fig. 2k), the comparison of the signals in Fig. 2g, k, l and m, it can be seen that the formation of the fe transitions of the decoded signal occurs after the phase of the clock signal (closure of the D flip-flop 14, Fig. 2n at the moments of the transition of the clock signal from the low potential to the high

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five

Claims (1)

Invention Formula A device for receiving a relative bi-pulse signal, containing a one-shot, serially connected RS flip-flop and D-flip-flop, a clock shaper and serially connected input matching unit, an amplifier and a transition lock, the output of which is connected to the single-shot input of the restart and to the first input of the And element , characterized in that, in order to increase the reliability of reception with a high level of interference, a front selector, a clock phasing unit, a logic unit and a quartz auto signal are introduced The generator, the output of which is connected to the synchronization input of the register, the information input and the outputs of which are connected respectively to the output of the one-shot with restarting, which is connected to the input of the edge selector, and to the inputs of the logic unit whose output is connected to the S-input of the RS flip-flop, The R-input of which is connected to the corresponding output of the register, while the output of the edge cutter is connected via the one-shot to the second input of the AND element, the output of which is connected to the first input of the clock-phase phasing unit, W The input of which is connected to the output of the clock signal generator, the input of which is connected to the first input of the element I, and the output of the clock phasing unit is connected to the synchronization input of the D-flip-flop. jnjnjiJi rTnj-bFLi4JajiJT n  L Fig, 2