SU1211849A2 - Digital frequency discriminator - Google Patents

Abstract

This invention relates to radio engineering i In relation to auth.St. No. 849419 increases accuracy with equality of compared frequencies. The device contains four JK-flip-flops 1.2 ,, six elements And 3, 4,5,6,7,8, two sync blocks 9, 10, RS-flip-flop II and inverter 14. The operation of the device is considered for three cases of periods of input signals: TUT2, and. If TUT2, then the differential pulses coming through the input bus 18 will pass to the output bus 21. If, then the differential pulses coming through the input bus 19 will pass to the output bus 24. The introduction of the LC triggers 12, 13 and the inverter 14 allowed improve accuracy with equal frequencies compared. 2 Il. W / 4 w Y e.}

Description

The invention relates to radio engineering and can be used in digital measuring devices and is an improvement of the digital frequency discriminator according to the author. St. No. 849419.

The purpose of the invention is to improve the accuracy with equal frequencies compared.

Fig. I shows a structural electrical circuit of the device proposed; FIG. 2 is a structural electrical sync circuit diagram.

Digital frequency discriminator contains the first and second ZK triggers 1 and 2, six elements And 3-8, two sync blocks 9 and 10, RS-trigger 11, two additional ZK-triggers 12 and 13, inverter 14.

The sync block 9 (s) contains two K-triggers 15 and 16, ale: -7t AND-NOT

Digital frequency discriminator works as follows.

Consider the case when TKT2. With the arrival of a negative differential over bus 18, the LC trigger 1 is set to one. If a negative differential does not appear on bus 19 before a positive differential arrives on bus 18, then

the appearance of a positive differential across bus 18 at the output of element I 3 appears to be negative, resulting in a 3k-flip-flop 5 (figure 2) becoming one. With the arrival of a clock pulse TI t via bus 20 EC-flip-flop 16 goes into a single state, then, due to fault 21, a clock pulse arrives and prepares the transition of the OK trigger 13 to the single state, since the outputs 01–34 and C have single signals. At output 22, this pulse does not pass, because ZK-flip-flop 13 is not yet in the zero state, after which the bus 23 um clock TOF and through AND-NO element 17 sets the flip-flops 1 and ZK- 15 in null state, and ZK-flop 13 through an inverter 4} in a unit. The next clock pulse TI sets the LC trigger 16 to the zero state. . The next negative differential over bus 18 sets LC-trig-jrep 1 to one, the state. If a

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 on bus 19, a negative differential does not occur until a positive differential arrives on bus 18, the appearance of a positive differential on bus 18 at the output of the element I 3 appears to be negative, causing Ek-flip-flop 15 to become one. With the arrival of the clock pulse TI1 via bus 15, the Ek trigger / 16 goes into one state, after that the tapping impulse TI2 comes through bus 22 and passes through element 7 to exit 11, then

3k-triggers 1.15 and 16 are returned to the initial (zero) state.

Prior to the arrival of a negative differential along the bus 19, all subsequent 11 Ie positive drops on the bus 18

are similarly converted and passed through AND 7 to exit 21.

Now, let us first receive a negative differential over bus 18, which sets the JK-trigger 1

In the unit state and before the positive differential arrives on the bus 18, the negative difference on the bus 19 comes, which sets the RC-flip-flop 2 into one state, then at all inputs of the AND 4 element are logic I, the output of this element is logical O, which sets the RS - trigger 11 in a single state, and

the level from the zero output of the RS flip-flop 11 sets the Zk-flip-flops 1 and 2 to the zero initial state.

Suppose now that the negative differential arrives on the bus 19 and before the negative differential arrives on the bus 18 a positive differential arrives on the bus 9. At the output of the element I 6, the logical level

the zero that sets the JK-trigger 15 of the second sync block 10 to single state. With the arrival of the THl-no clock pulse, the 20-clock trigger 16 of the second sync block 10 is set to the single state. The next clock pulse TI2 on the bus 22 prepares the setting of the RS flip-flop 11 to the zero state, since at the input of the 32-ZK flip-flop 13

the logic level is O, and on all the K-inputs the logic level is 1. The next clock pulse of the SIZ sets 3K-triggers 2. 15 and 16

The second sync block 10 is in the zero state and the entire digital frequency, the itbivL discriminator, is in the initial state. Consider the case when. Let the negative differential first come along bus 18 and set the LC-trigger 1 into a single state. If a negative differential across bus 19 arrives before a positive differential arrives through bus 18, then at all inputs of the AND 4 unit there are single signals, its output is a zero signal, which sets RS flip-flop II to one state, the zero output of which goes to the zero state and. rejects the tJK triggers I and 2 to the zero state. At the zero outputs of the Zk-flip-flops 1 and 2, the levels of the logical unit that translate the output of the element And 5 to the zero state and set the RS-flip-flop 11 to the zero state. If a negative differential across bus 19 arrives after a positive differential arrives at bus 18, then by a positive differential across bus 18, first the sync block 9 is set to one and translates to clock pulses TI2 and TIZ EC trigger 13 into one state, and then the bus 19 receives a positive differential, through which the second sync block 10 is triggered and, by clock pulses TI2 and TIZ, the EK trigger 13 again returns to its original, zero state.

If the bus 19 does not have a positive differential before the arrival of the second negative differential on bus 18, then the K-flip-flop 13 remains in one state, and the ZK-flip-flops 1 and 2 are set to zero with the signal from the zero output of the RS-flip-flop 1 I.

Consider the case when TIM2. Let the device be in its original state, i.e. ZK-trigger 12 in one state, and all other triggers in zero, With the arrival of a negative differential on the bus 19, Zk-trigger 2 is set to a single state. If the negative differential on bus 18 arrives before the positive differential arrives on bus 19, then ZK trigger 1 will also be set to one, and RS-trigger 1I will first set Zk-tri11849

Ger 1 and 2 to the zero state, and then through the element And 5 itself will be established in the initial, zero state. Now let positive differential 5 through bus 19 come before negative differential through bus 18, then at the output of element And 6 a zero signal, which sets the EC trigger 15 of the second 10c sync block.

10 single state. The next tactical impulse TI1 on bus 20 sets the ZK trigger 16 of the second syncro, block 10 to one state. The clock pulse TI2 on the bus 22 under 15 prepares the ZK trigger 12 to be set to zero, since all inputs K of the LCD trigger 12 have a logic level of 1, and input J2 has a logic level of zero.

20 A TIZ clock pulse across bus 23 sets JK triggers 2, 12, and 15 to the zero state. The next clock pulse TI sets: tJK-trigger 16 to zero position,

25 All subsequent pulses in chic 19 after conversion in the second sync block e 10 through the clock pulse TI2 through the bus 22 are received through the element I B on the trick of 24 to those

jg until another negative differential over bus 18 arrives, If the negative differential across bus 18 arrives before another positive differential arrives on bus 19, then the tlK triggers 1 and 2 are set to the zero state by the signal from the zero output K5-trigger : - Pa. If a negative differential across bus 18 arrives after another positive differential arrives on bus 19, then, or when a positive differential arrives on bus 18, the first sync block 9 will work and translate Zk-flip-flop 12 into a single one, and ZK-triggers 1, 15 , 16 to zero, initial state ue. or with the arrival of the next negative differential over bus 19, Zk-trigger 2 is set to one and RS flip-flop 11 sets K-triggers 1 and 2 to zero state 0, after which RS-flip-flop 11 returns to zero, initial state ni

Thus, if TKT2, then the differential pulses, coming through bus 55, are transmitted to the output bus 2G. If, then the differential pulses, coming along bus 19, are passed to the output bus 24.

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Claims (1)

Formula from t Digital frequency discriminator auth. St. No. 849419, about tl and h and rani and with the fact that, with a chain of improved accuracy with equality of the compared frequencies, two additional tJK triggers and an inverter are introduced into it, the input of which is connected to the third bus of clock signals, and the output is synchronization outputs of additional ZK-triggers, with the first 3 and K-inputs of additional ZK-triggers connected to the second bus clock signals, the second. 3 inputs of additional K-flip-flops with the second input of the first sync block, third E-inputs of additional EC-flip-flops with a direct output of the first Qc-flip-flop, second K-inputs 12118496 Additional tlK-flip-flops are connected to the direct output of the second ZK-Trigger, and the third K-inputs of the additional ZK-trigers are connected to the second input 5 of the second sync block, while the direct outputs of the first and second additional Zk-triggers are connected respectively with the first and second inputs of the first output element fO Ie the second additional input of which is connected to the fourth 11 — the input of the first additional LC-trigger 5 and the inverse outputs of the first and second additional LC-trig 15 geers are connected respectively to the first and second additional inputs of the second output element I, the first additional input of which is connected to the fourth K-input of the second 20 additional JK-flip-flops, R FIG. I Compiled by I. Grabilin Editor L. Avramenko Tehred O. Vashchishina Proofreader V. But ha Order 649/59 Circulation 818 Subscription VNRPSHI State com1; -1teta USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch 1Sh1 Patent, Uzhgorod, st. Project, 4