GB1355495A - Apparatus for clocking digital data - Google Patents

Abstract

1355495 Digital transmission; synchronizing A C COSSOR Ltd 18 Aug 1971 [18 Aug 1970] 39797/70 Heading H4P To reconcile the phase of clock pulses with that of input data, a number of phase displaced clock synchronous wave forms are generated, one of which is selected nearest to the phase of input data. Such arrangement is particularly suitable for equipment having a delay line the characteristics of which may change with time and/or temperature. The arrangement may be applied to various types of data modulation, i.e. NRZ, RZ, bipolar or phase reversal. The input data clocked by a timing system 18 is passed through a delay line 12 and buffer stage 20 which may be a limiting amplifier or an amplifier followed by a Schmidt trigger circuit, the output being clocked to a flip-flop 22, e.g. D type before entering a utilization apparatus 16. If the output 28 of system 18 is fixed and passed directly to a flip-flop 22, while some tolerance in the instance of arrival between these pulses and those from delay line 12 is permissible, at some point errors will occur. This system is known in the art. The disclosure resides in the provision of a number of phase displaced pulse trains synchronized with timing system 18, an appropriate train being selected by a decoder 48 and passed by line 26 to flip-flop 22. Selection is determined by a differentiator 36 which is sensitive to either negative or positive going edges from buffer 20 and produces negative going spikes at its output which are applied to an R-S flip-flop formed by gates 38, 40 also receiving pulses 28, the output being passed through an AND gate 46 enabled only when R-S is reset, thus after the reference pulse has finished a counter 44 will be pulsed through its states starting from zero which will continue until a spike from differentiator 36 resets R-S which locks the clockpulses to the counter thus the count is indicative of the interval between the back edge of the reference pulse and the next positive or negative data edge respectively. The count is recognized by decoder 48 and the appropriate input from 18 is selected and routed to flip-flop 22. Differentiator 36 may be omitted but the amount of compensation possible will be reduced. As the timing of flip-flop 22 is arbitrary with reference to the clock pulses in the block 16, a second flip-flop 32 may be inserted and receives a signal of constant phase displacement from system 18. As the short term stability of a delay line is normally good, reference pulses may be applied with relative infrequency. A simpler arrangement is described with reference to Fig. 3 (not shown). Data is circulated round a delay line twice i.e. incoming bits are interleaved with bits circulating a second time and split at the output of the line by two flip-flops, which are clocked with different pulses; a compensation circuit may be adapted to this type of configuration. This employs a third flip-flop (52) and a switch (54) which diverts alternate ones of double rate pulses to flip-flop (52) and the other alternate ones to flipflop 22.