SU1187145A1 - Device for holding zero crossings of periodic signal - Google Patents

Abstract

1. DEVICE FOR FIXING TRANSITIONS THROUGH ZERO.;. A PERIODIC SIGNAL containing output buses, an input source, a square pulse shaper connected by a first input to an input source, a zero zone gap shaper connected by the first and second inputs to the first and second outputs of a square pulse shaper, respectively impulses connected by the first input to the second output of the rectangular impulse generator, the first counter connected by the installation input to the first output f a control pulse liter, a clock pulse generator, connected by an output to the third input of the zero zone interval generator, and a second counter, characterized in that, in order to improve the accuracy of fixing the zero crossing points of the distorted periodic signal, two code-time spans are entered into it and combinational adder, connected by direct information inputs to information outputs of the first counter, and inverse ones, except the oldest one, connected to a zero base To the information outputs of the second counter with a shift by one bit towards the senior, the installation input of which is connected to the output of the zero zone interval former, while the counting inputs of both counters are connected to the additional output of the clock generator, with the third input of the square rectangular pulse generator, with the third inlet house 59 of the driver control pulse generator and with the first inputs of the first (L. and the second converter of the code-voltage: interval, connected by the second and third inputs, respectively, with the second and third outputs of the driver for controlling pulses, the fourth input of which is connected 00 to the first output of the driver of rectangular pulses and the fourth inputs of the code-time converter 1 interval are connected to the output of the sum of the combinational adder, with the second input of the driver of control pulses connected to the output of the clock generator, the outputs of the time code converters The shaft is connected to the first and second output buses, respectively, and the output of the clock pulse generator is connected to the second input of the square pulse generator. 2. A device according to claim 1, characterized in that the former of the square pulse

Description

The invention relates to a pulse technique and can be used to build devices. ' for measuring the frequency and phase in control devices of thyristor converters 5 operating from the mains, the voltage form of which is strongly distorted.

The purpose of the invention is to increase the accuracy of fixing the moments of transitions Yu through zero of a periodic signal, including a distorted one.

Figure 1 shows a structural diagram of a device for fixing the transitions through zero of a periodic signal: 15 in Fig.2 - 5 structural diagrams of a rectangular pulse shaper, a zero-zone interval shaper, control pulse shaper and a code-time interval converter; in FIG. 6 is a timing diagram explaining the operation of the device.

The device for fixing transitions 25 through zero of a periodic signal contains an input signal source 1, a clock pulse generator 2, a rectangular pulse shaper 3 connected by a first input to an input signal source 1, a second and third inputs, respectively, with an output and an additional output of a clock pulse generator 2, a shaper 4 intervals of the zero zone, connected by the first and second 35 inputs respectively with the first and second outputs of the shaper 3 rectangular pulses, the third input with the output of the generator and 2 'clock Pulses, driver 5 5 control pulses, respectively connected by the first and second inputs to the second outputs of the driver 3 rectangular pulses and an additional output of the generator 45 2 clock pulses, the first counter 6, connected to the input of the installation R with the first output of the driver 5 control pulses, counting input - with an additional output 50 of the generator 2 clock pulses, the second counter 7, connected to the input of the installation R with the output of the shaper 4 intervals of the zero zone, the counting input - with an additional '55 output of the generator 2 clock pulses, a combinational adder 8 connected by direct information inputs with information outputs of the first counter 6 and inverted, except the oldest, with information outputs of the second counter 7 with a shift by one digit in the direction of the older, the first 9 and second 10 code-time interval converters connected by the first inputs to the additional output of the 2 clock pulse generator, while the second and third inputs of the code-time interval converters are connected respectively with the second and three outputs of the driver 5 of the control pulses, and the outputs of the converters 9 and 10 code-time interval are connected respectively to the first 11 and second 12 output · buses, and the driver 3 of the rectangular pulses contains a voltage reference 13 and two comparators 14 and 15, the first inputs of which are connected to the first input of the driver 2 rectangular pulses, the second inputs, respectively, to the direct and inverse outputs of the source 13 of the reference voltage, and the outputs to the information inputs of the first and second D-trigger 16 and 17, direct which outputs are connected to the information inputs of the third and fourth O-flip-flops 18 and 19.

Shaper 4 intervals of the zero zone contains an OR element 20., The output is connected to the information input of the D-trigger 21, the shaper 5 of the control pulses contains an RS-trigger 22, the direct output of which is connected to the information input of the first D-trigger 23, a direct output connected to the information input second trigger _? 24, the direct output of which is connected to the information input of the fourth D-flip-flop 25, while the direct output of the RS-flip-flop 22 and the inverse output of the first D-flip-flop 23 are connected to the first and second input of the first element 3 AND 26, the inverse output of the RS-flip-flop 22 and the direct output of the first D-trigger 23 is connected to the first and second input of the second element of the ZI 27, the direct output of the second D-trigger 24 is connected to the first input of the element of the ZI-OR 28 element, the code-time interval converter contains a D-trigger 29, you ^{3 11} moves connected to the first input of the element And 30, you the course of which is connected to the counting input of the subtracting counter 31, information outputs connected to the information inputs of the decoder 32 zero. counter status.

The device operates as follows.

The input signal from source 1 is input to the shaper 3 of rectangular pulses (FIG. 1), and therefore, to the inputs of the comparators 14 and 15 (FIG. 2), where in the first it is compared with a positive threshold voltage, and in the second with a negative one.

When the positive half-wave of the input signal exceeds the positive threshold voltage (intervals t _o - t /, t „- t ₄ - tp t ^ - C-, Fig.6), the positive voltage appears at the output of the first comparator 14, which is taken as the logical level units a 1 = 1, while the output of the second comparator 15 is the level of logic 0. When the negative half-wave exceeds the negative threshold voltage (intervals t _a -C, t _fe - t ₆ , t ~ b ₇ , Fig.6), the output of the second comparator 15 appears logical level 1 (B1 = 1>. When the input signal is between voltage, i.e., the zero zone, the output of both comparators 14 and 15 will be zero voltage, i.e., the logic level is 0. The output signals from the comparators are fed through two-bit shift registers made on D-flip-flops 16, 18 and 17 , 19. This is due to the fact that for reliable operation of the counters, for which the counting inputs of the triggers included in them are combined, it is necessary that the counting pulses are not shortened at the front and at the slice of the count resolution pulse (pulse transmitting counting pulses to the counter). th pulse be part of the switch triggers *, the smaller the speed can not switch, which will cause a large error counter code.

To prevent this from happening, it is necessary that the front and the slice of the resolution pulse are between the counting

145 4 pulses. For this, it is necessary that the output signals of the comparators 14 and 15 along the edge and slice coincide with the front or slice of the clock pulses. Such a temporary binding of the signals of the comparators 16 and 15 to the clock pulses was carried out on D-flip-flops switching along the front of the clock pulse. The first snap on the D-flip-flops 16 and 17 is on the front 01, and the second on the D-flip-flops 18 and 19 - on the front 02. A double snap is more reliable than a single one when there are oscillations on the edges of information and clock signals. Time reference is necessary for generating at certain moments of the input signal control pulses and intervals, the edges and slices of which coincide (accurate to the delay of the elements) with the edges and slices of clock pulses ..

Logical signals a3 and b3 (Fig. B) from the outputs of the D-flip-flops 18 and 19 have the same repetition period as al, b1, (Fig. 6), but their front and slice coincide with the front of pulses C2. the higher the pulse repetition rate as compared with the input signal repetition rate, the smaller the shift of signals a3 and b3 relative to a1, b1 and their difference in duration. Therefore, the real relative shift will be several orders of magnitude less than that shown in Fig.6.

Logical signals a3, b3 (Fig.6) from the output of the shaper 3 of the rectangular pulses are fed to the inputs of the shaper 4 intervals of the zero zone and the shaper 5 of the control pulses.

In the shaper of 4 intervals of the zero zone from the signals a3, b3 on the element OR 20 An inverse signal is formed e1 = a3 + b3 = a3 b3, the front and cut of which coincide (without taking into account the delay of the microcircuits) with the front of C2. On the D-flip-flop 21, the signal e1 is shifted along the slice of the pulse C1, due to which the signal e2 overlaps the pulses £ 1 and ¢ 2, which coincide with C1.

In the shaper 5 of the control pulses (Fig. 4), the logic signal of the shifted half-periods d1, the front and the slice of which is 118714 5 aZ, is formed from the signals АЗ, ВЗ on the RS-flip-flop 22

Figure 1

.1187145 g * 'ι

Fig.Z

Fig. C

Figure 5

FIG. IN

Claims (6)

one contains the bottom of the comparator, the combined first inputs of which are the first input of the square pulse generator, the reference voltage source connected to the direct and inverse outputs with the second inputs of the first and second comparators, four D - flip-flops, the information inputs of the first two of which are connected respectively the outputs of the first and second comparators, and the direct outputs - to the information inputs of the third and fourth D - flip-flop, the direct outputs of which are the first and second outputs form l rectangular pulses, the clock inputs of the first and second, third and fourth V - triggers} are respectively the second and the third input of the direct moulngh pulses. 3. The device according to claim 1, characterized in that the zero zone interval former contains an OR element whose inputs are the first and second inputs of the zero zone interval shapator, D trigger, connected by an information input to the OR element output, the D-trigger synchronization input is By the third input of the shaper of the zero-zone intervals, and the exit is the exit of the shaper of the zero-zone intervals. 4. The device according to claim 1, characterized in that the driver of the control pulses contains a Q-trigger, R - and 5 - whose inputs are respectively the first and fourth inputs of the driver of the pilot pulses, three O - flip-flops, and the first outputs of the first and the second O - triggers are connected to the information inputs of the second and third O - triggers, respectively, and the direct output R5 of the trigger is connected to the information input of the first D-trigger, the first and second elements of the GI connected by the first inputs to the direct and inverse outputs R5 of the trigger, respectively, the second inputs to the inverse and direct outputs of the first C-trigger, and their outputs are the second and third outputs of the control pulse generator, the ZI-OR element, the output of which is the first output of the control pulse generator, while the first and second ZI elements of the ZI-OR element are connected to the direct and the inverse outputs of the second and third D-flip-flops; the inverse and direct outputs of the second and third D-flip-flops; the synchronization input of the second-flip-flop is the third input of the control pulse generator; the synchronization inputs of the first and third L-flip-flops are the second input of the control driver pulses and are connected to the third inputs of the elements ZI and the third inputs of the elements ZI of the element ZI-OR. 5. The device in accordance with claim 1, 1, 1 and 2, the code-time interval contains D - trigger 5 and the R inputs of which are the second and third inputs of the converter, respectively, the time interval, and the information O - input is connected to a zero-potential bus element And connected to the first input with an output and -trigger, and the second input of the element I is the first input of the code-time interval of the converter, subtracting the counter with the pre-recording, whose information input is the fourth input of the transducer the code-time interval developer. the input of the record is connected to the R input of the 3) trigger, and the counting input with the output of the And element, the decoder of the counter zero state, connected with the information inputs with the information outputs of the counter, the input of the gating - with the second input of the And element, and output - with the synchronization input of the D-trigger and the output of the code-time interval converter. ryh coincides with the front of C2. The signal d1 is equal to logical 1 during the intervals tp-t, tg, etc. and logical O during the intervals t, tg (up to a shift). Further, on the shift register on D-flip-flops 23-25, the signal d1 is shifted three times to receive signals d2, d3, d4, with which the code recording pulses are generated from the output of the combinational adder 8 to the converters 9 and 10, the time interval and the pulse are set to zero counter 6. The first shift on D-flip-flop 23 is carried out along slice C1, the second - at D-flip-flop 24 along front C2, and the third - on Dtrigger 25 also along slice C1. On the ZI element 26 pulses are formed, coinciding with ClC d1 d2) and appearing at times t, C, t with a shift delay. Similarly, on the element ZM 27 i) 2, C1-dld2 appears with a Delay on shifts at times tj, tg, etc. On the element 2-ZI-1ILI 28 a SZ pulse is formed, which coincides with the pulse C1 and is delayed relative to t 1 and t 2 by one period C1. The counting pulses for counters 6 and 7 are C2 clock pulses (Fig. 1.10). The difference between the contents of the counter 6 and the half of the contents of the counter 7 is obtained on the combination adder 8 operating in the subtraction mode. The division of the contents of counter 7 into two is accomplished by a constant (assembly) shift of the contents of the counter by one bit to the right (in the direction of the lines). In this case, the lower bit of counter 7 is not used, and the upper subtractive input of the adder 8 is supplied with a logical O. The output of the sum of the combination adder 8 is connected to the information inputs of the converters 9 and 10, the time interval, therefore, the information inputs of the preliminary recording of the subtracting counter 31, the recording of which record impulses are received about 1 2). Each converter is a time interval, except for subtracting counter 31, contains a zero-state de-diffractor 32 counter, D-flip-flop 29 with settings, and element 30. Currently, instead of a separate subtracting 5 counter and a zero-state decoder, a reversible counter can be used with built-in decoder of the zero and one states of the counter, which is available in the series of microcircuits TTL (K155IE7. 133IE7) and K-MOP (K561IE11, 564IE11). The zero-state decoder 32 of the counter can be implemented 5 with direct counter outputs on an OR-NOT logical element with an inverse input for stitching from C (c4) A1 ... Apn-LG. ... The trigger 29 and the element 30 form a valve for passing the clock pulses C2 to the counting input of the subtracting counter 31. The output pulses are removed from the output of the decoder 32. 5 Consider the operation of the device:; tva in time. Let at time tg (Fig. 6) the input voltage exceeds a positive threshold, resulting in 0, the output of the comparator 14 is a logic level 1 (), which is shifted by the D-flip-flop 16 along the front of C1 (), and at the D-flip-flop 18 - along the front of C2 (). At time t, the input voltage becomes less than the positive-Threshold, the output of the comparator 14 again appears the level of logic O (), which also shifts along C1 0 () and C2 (). Similarly occurs at times t ,, t, t, t, t, tj, tg. When the negative half-wave of the input signal exceeds the negative threshold, the level 5 logical 1 appears at the output of the second comparator 15 (in 1 1), which occurs at times t, t, tg, tg. When a negative half wave becomes less negative 0 threshold, logical level 1 on the output of the comparator 15 is replaced by the level of the logical O (, moments t, t, t, ty). Similar to a1 shift on D-triggers 17 and 19, occurs 5 shift of bipart b1 (). When the input voltage value is between threshold levels | at the outputs of both comparators 14 and 15 a logical O, According to a positive differential AZ at the time t (up to a shift), the RS flip-flop 22 (Fig. 8) switches to the state of logical i, and at the time t. (up to a shift) on the VZ to the logical O. state. Similarly, at times t, tjH, etc. Thus, the signal d1 is formed, which is equal to logical 1 during positive ps of shifted half-periods (t tg and so on) to logical O during negative shifted half-periods (tj - t, tg - tg, etc.). At time t, the write pulse. C1 rewrites the code D B, the subtracting counter 31 of the converter 10 is a code-time interval. In this case, the A code is proportional to the previous shifted negative half period; The B-code is proportional to the interval of the moments by the moments of the crossing of the threshold levels by the input signal. At the same time, impulse 1 in the same converter establishes Гьтри Гер 29 at the input R to the state of logical O, if for any reason it was in the state of logical 1, for example, during initial switching on. This prevents immediate reading of the recorded code. For pulse 1, counter 7 (figure 5) by signal e2 is reset to zero at input R and held at zero until e2 1 () Then, pulse S 3, counter 6 is reset to zero and the next pulse C2 starts again count, transform-positive shifted half-period to code. At the same time, by pulse 1, moment tg D-flip-flop 29 in converter 9 at input S is set to logical 1 (), thereby allowing the passage of pulses c2 through element T and 30 to the counting input of deducting counter 31. Thus, the code recorded in counter 31 converters into the previous shifted positive half-period (at the moment similar to the moment t) begins to transform into an interval. After passing through C pulses of C2 counts A - j, the chuck 31 is right: terminal 9 is set to state O (), the next (B + 1) -th pulse C2 passes through decoder 32 to output bus 11, and through element ZI 27 to the counter input of the counter 31. Slice (D +1) -th pulse 32, the counter 31 of the state O switches to state 1, the decoder 32 closes, stopping the passage of the pulse C2 to the output bus 11. Simultaneously, the slice (D + 1) The -ro pulse C2 transmitted through the decoder D-trigger 29 is set to the state O, thereby locking the element I 30 and stopping the access the pulse in C2, the counting input of counter 31. Thus, at time t, output pulse 11 has a pulse CW corresponding to the transition of the input signal from a positive to a negative value. During the interval t - t, when the converter 9 converts the code into the interval, the converter converts: the body 10 is in the storage mode, and the counters 6 and 7 are busy converting the C - t, by forming the intervals, respectively, into the code. In this case, the interval to - tg is the counter. 7 is not taken into account, since after the input signal leaves the zero (interthreshold) zone at time t, the counter is reset on the input R by the signal CHN.) E2 (Fig. 6). Starting from the moment t, the converter 10 converts the code recorded at the moment tg into the interval and sends a pulse c4 to the output bus 12 at the moment t. At this time, the converter 9 is in the storage mode of the code recorded by the pulse € 2 from the output of the combination adder 8 at time t. The process then repeats. 1 The invention relates to a pulse technique and can be used to build devices. for measuring frequency and phase in thyristor converter control devices. li mi operating from the mains supply, the voltage form of which is highly distorted. The purpose of the invention is to increase the fixation of the moments of zero crossing of the periodic signal, including the distorted signal. Fig. 1 shows a block diagram of a device for fixing a zero-crossing of a periodic signal: Fig. 2-5 shows block diagrams of performing a square pulse shaper, a zero zone shaper, a control pulse shaper, and a time-period converter; in fig. 6 - timing diagrams for the operation of the device. The device for fixing zero transitions of a periodic signal contains a source of 1 input signal, a generator of 2 clock pulses, a generator of 3 square pulses connected by a first input to a source of 1 input signal, the second and third inputs correspond to the output and an additional output of a generator of 2 clock pulses, driver 4 intervals of the zero zone, connected by the first and second inputs, respectively, with the first and second outputs of the imaging unit 3 rectangular pulses, the third input - with the generator output 2 ta 1 pulses, a driver of control pulses 5, connected respectively by the first and second inputs to the second outputs of a generator of 3 rectangular pulses and an additional output, a generator of 2 clock pulses, the first counter 6 connected by an input of the R installation to the first output of the generator of 5 control pulses, a counting input - with an additional output of the generator 2 clock pulses, the second counter 7 connected by the input of the installation R with the output of the generator 4 intervals of the zero zone, the counting input - with the additional output generator 2 clock pulses, combinational adder 8, connected by direct informational inputs with information outputs of the first counter 6 and inverse, except the senior, with information outputs of the second counter 7 with a shift by one bit in the direction of the older, first 9 and second 10 converters code -time interval . The first inputs with an additional generator output 2 clock pulses, while the second and third inputs of the code-time interval transducers are connected to the second and third outputs of the driver 5 control pulses, respectively, and the outputs of the transducers 9 and 10 code-time interval are connected respectively to the first 11 and the second 12 output buses, the shaper 3 of rectangular pulses contains the source 13 of the reference voltage and two comparators 14 and 15, the first inputs of which are connected to the first input of the form The gateway has 2 rectangular pulses, the second inputs are respectively to the direct and inverse outputs of the source 13 of the reference voltage, and the outputs are connected to the information inputs of the first and second D trigger 16 and 17, the direct outputs of which are connected to the information inputs of the third and fourth -trigger 18 and 19. The shaper 4 intervals of the zero zone contains the element OR 20, the output connected to the information input of the D-trigger 21, the shaper 5 control pulses contains the RS-flip-flop 22, the forward output of which is connected to the information input of the first D - flip-flop 23, direct output connected to the information input of the second D-trigger 24, the direct output of which is connected to the information input of the fourth D-flip-flop 25, with this output K & Trigger 22 and the inverse output of the first D-trigger 23 connected to the first and second inputs of the first element 3 And the 26.9-inverted output of the RS trigger 22 and the direct output of the first D trigger 23 are connected to the first and second inputs of the second element ZI 27, the direct output of the second D-trigger 24 is connected to the first input element ZI element ZI-OR 28, the converter code- Belt span includes D-flip-flop 29, vy3 swing coupled to a first input of AND ele fenta 30, whose output is connected to the counting input of down counter 31, data outputs connected to data inputs of the decoder 32 of zero. counter status. The device works as follows. The input signal from source 1 is fed to the input of the shaper 3 of rectangular pulses (Fig. 1) and, therefore, to the inputs of Comparators 14 and 15 (Fig. 2), where in the first it is compared with a positive threshold voltage, and in the second with a negative one. When the positive half-wave of the input signal exceeds the positive threshold voltage (integrals t ,, t, t |, ttf t., FIG. 6), the output of the first comparator 14 also shows a positive voltage, which is taken as level vei logical unit. In this case, at the output of the second comparator 15, the level of the logical O. When the half-wave is negative exceeds the negative threshold voltage (intervals tj - t, j, t - t, t, t - tJ., FIG. 6), the output of the second comparator 15 is level of logic G (. When the input signal is between threshold voltages, i.e. zero zone, the output of both comparators 14 and 15 will be zero voltage, i.e. the level of logic O. Output signals from the comparators go through two times common shift registers performed on D-flip-flops 16, 18 and 17, 19. This is due to the fact then for reliable operation of counters in which the counting inputs of the flip-flops entering into them are combined, it is necessary that the counting impulses do not shorten at the front and cut of the counting resolution pulse (the pulse of the counting pulses into the counter). a lower speed may not be switched, which will cause a large error in the counter code. In order for this not to happen, it is necessary that the front and cut of the resolution pulse be between the counting 54 pulses. To do this, it is necessary that the output signals of the comparators 14 and 15 on the front and the slice coincide with the front or cut of the clock pulses. Such a time assignment of the signals of the comparators 16 and 15 to the clock pulses was carried out on 1-1 tigers switching along the front of the clock pulse. The first tie-in on D-flip-flops 16 and 17 is on front C1, and the second on D-flip-flops 18 and 19 on front C2. Double bindings are more reliable than single bindings when there is oscillation on the fronts of information and synchronizing signals. The time reference is necessary, the formation at certain moments of the input signal of control pulses and intervals, the fronts and cuts of which coincide (up to a delay of elements) with the fronts and cuts of clock pulses. Logic signals AZ and E3 (fig.b) from the outputs D -triggers 18 and 19 have the same follow-up period as a1, b1, (Fig. 6), but their front and section coincide with the front of C2 pulses. At the same time, the Bbmie the frequency of the clock pulses in comparison with the frequency of the input signal, the smaller the shift of signals AZ, VZ relative to a1, B1 and the difference in their duration. Therefore, the actual relative shift will be several orders of magnitude smaller than that shown in FIG. The logic signals AZ, VZ (Fig. 6) from the output of the former 3 rectangular pulses are fed to the inputs of the former 4 intervals of the zero zone and the former 5 control pulses. In the imaging unit, there are 4 intervals of the zero zone of the signals AZ, VZ on the element OR 20 frmi de inverse signal 1 AZ and BZ ASV1, the front and the section of which coincide (without taking into account the delay of the microcircuits) with the front C2. On the B-flip-flop 21, the signal el shifts across the slice of the pulse C1, thanks to which the signal e2 blocks the pulses 1 that coincide with C1. In the driver 5 of the control pulses (Fig. 4), the logical signal of the shifted half-periods d1 is formed from the signals AZ, VZ on the RS-flip-flop 22, the front and section of which 12 Fig.Z 5