RU1793545C - Converter from code to pulse-width signal - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in digital drive control systems. The purpose of the invention is to expand operational capabilities by increasing the reliability of information when changing the input code. The goal is achieved in that the code converter is a pulse-width signal, the first through fourth AND-NOT elements, the first, second and third triggers, the second register and pulse counter, the fifth AND-NOT element, the OR, AND, OR elements - NOT, the first, second and third inverters, the information inputs of the first and second registers are the input code bus. 2 ill.

Description

The invention relates to automation and computer technology and can be used in digital drive control systems.

A known code converter in time interval 1. comprising a pulse generator, first and second pulse counters, first and second triggers, AND, OR elements, a pulse distributor and an inverter unit. The disadvantage of this converter is that after each code conversion into a time interval, a repeated trigger signal is necessary, even if the conversion code does not change.

Closest to the proposed device is a PWM-2 code converter. It contains a pulse generator, first and second triggers, a register, the information inputs of which are the corresponding input code buses. and the outputs of the bits, except for the older one, are respectively connected to the information inputs of a reversible counter, the first and second outputs of which are respectively connected to the S- and R-inputs of the first trigger, and also contains a digital delay element, an adder modulo two, the first, second, third and a fourth AND-NOT element and a third trigger, the D-input of which is a zero potential bus. The C-input is combined with the C-input of the second trigger, the inputs of zeroing the register and the reverse counter and is the Initial setting bus, and the R-input is connected to the first overflow output of the reverse counter, the second overflow output of which is connected to the R-input of the second trigger, information input high-order - with the inverse high-order output of the register, and the summing and subtracting inputs are connected to the outputs of the third and fourth AND-NOT elements, respectively, the first inputs of which are respectively connected to the direct outputs of the second and second triggers and are the first and second output

ate

with

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buses, and the second inputs are combined with the first input of the digital delay element and connected to the output of the pulse generator, while the output of the adder modulo two is connected to the recording enable input of the reverse counter, and the first and second inputs are combined with the second and third inputs of the digital delay element and connected to the inverse outputs of the second and third triggers, the S-inputs of which are respectively connected to the outputs of the first and second elements AND NOT, the first inputs of which are combined and connected to the digital output lementa delay, and second inputs respectively connected to the direct and inverse outputs of the first flip-flop, and a register write enable bus output is recording, and D-input of the second flip-flop - setting a logic 1 bus.

The disadvantage of this converter is that the device controlling its operation cannot write a new conversion code to the register at the moment when the code from the register is written to the counter, i.e. the device does not allow changing information on the input bus at any time. Otherwise, the counter may be set with the wrong code and the code-to-PWM conversion does not work correctly.

The aim of the invention is to expand operational capabilities by increasing the reliability of information when changing the input code.

The goal is achieved in that in the converter containing the pulse generator, the first register and pulse counter, the first to fourth AND-NOT elements, the first, second and third triggers, the direct output of the second of which is the first output bus, and the direct output the third trigger is the second output bus, and the S-input of the first trigger is connected to the transfer output of the first pulse counter, the first input of the first element is NOT connected to the output of the pulse generator, and the output is to the summing input of the first pulse counter, information the inputs of which are connected to the corresponding outputs of the first register, the information inputs of which are the input code bus, and the write input is the first bus. Register register, the pulse counter reset input is the bus. Initial setting, the second register and pulse counter are entered, the fifth element is And NOT, elements OR, AND, OR NOT, the first, second and third inverters, the information inputs of the second register being the input code bus and the outputs connected to the corresponding information inputs of the second pulse counter, the reset input of which is the Initial Installation bus, and the summing input is connected to the output of the first AND-NOT element, the first input of the AND element is connected to the output of the pulse generator, and the output is connected to the first input of the second AND-NOT element

0 the output of which is connected to the C-input of the third trigger, the inverse output of which is connected to its D-input and combined with the installation inputs of the first and second pulse counters and with the C-input of the first

5 a trigger whose inverse output is connected to the second input of the first AND-NOT element, the first input of the OR element and the first input of the OR-NOT element, and the direct input is connected to the first input of the fifth element

0 AND-NOT, whose output is connected to the first input of the fourth AND-NOT element, the output of which is connected to the second input of the fifth AND-NOT element and to the second input of the OR element, whose output is connected to the second

5 to the input of the second AND-NOT element, the transfer output of the second pulse counter is connected through the third inverter to the C-input of the second trigger, the S-input of which is connected to the transfer output of the first pulse counter and

0 combined with the input of the first inverter, the output of which is connected to the second input of the OR element, the output of which is connected to the second input of the element AND, the R inputs of the first, second and third triggers are connected and connected to the output of the second inverter, the input of which is the bus Initial installation, the D inputs of the first and second triggers are a zero potential bus, the second input of the second register is the second bus. Register is combined with the first input of the third AND-NOT element, the second input of which is combined with the recording input Vågå register, and an output coupled to a second home vho5 fourth AND-NO element.

A comparative analysis of the proposed device with the prototype shows that the proposed device is characterized by the presence of new elements: a second register,

0 of the second counter, elements AND, OR, OR-NOT, AND-NOT, inverters. Thus, the proposed device meets the criterion of novelty.

Comparison of the proposed solution does not

5 only with a prototype, but also with other technical solutions in the art, shows that the elements AND, OR, OR-NOT, AND-NOT, register, counter, inverter are widely known. But their introduction in this connection with other elements of the circuit

leads to the appearance of a new property: information on the input bus can be changed at any time. This allows us to conclude that the criterion is significant differences,

In FIG. 1 is a structural diagram of an inventive converter; in FIG. 2 are diagrams illustrating his work.

Converter code - pulse-width signal contains a pulse generator 1, register 2, counter 3, first 4, second 5, third 6 and fourth 7 element NAND, bus 8 of the input code, first bus 9 Write register, bus 10 Initial installation, first 11, second 12 and third 13 triggers, the direct output of the second trigger 12 being the first output bus 14, and the direct output of the third trigger 13 being the second output bus 15, the installation input of the first trigger 11 is connected to the counter transfer output 3 , the first input of the first element AND NOT 4 is connected to the generator 1 imp pies, and the output goes to the summing input of counter 3, the installation inputs of which are connected to the outputs of register 2, the inputs of which are connected to bus 8 of the input code, and the recording input is connected to the first bus. Register 9, the reset input of counter 3 is connected to the bus. Initial setting 10 . The second register 16, the second counter 17, the fifth AND-NOT 18 element, the OR 19, AND 20, OR-NOT 21. elements are entered into the converter. The first 22, the second 23 and the third 24 inverters, the second bus. Register register 25. Moreover bus 8 of the input code is connected to the inputs of the second. register 16, the outputs of which are identical with the inputs of the second counter 17, the reset input of which is connected to the bus. The initial setting is 10, and the summing input is connected to the output of the first AND-NOT element 4. The first input of the AND 20 element is connected to the pulse generator 1, and the output is connected to the first input of the second AND element -NOT 5, whose output is connected to the C-input of the third trigger 13. The inverse output of the latter is connected to its D-input, connected to the installation inputs of the first 3 and second 17 counters and to the C-input of the first trigger 11, whose inverse output is connected to the second the input of the first element And E 4, the second input of the OR element 19 and the first input of the OR-NOT 21 element, and the direct output is connected to the second input of the fifth element NAND 18. The output of the NAND 18 elements is connected to the second input of the fourth AND-NOT 7 element, the output of which is connected to the first input of the fifth element AND-NOT 18 and to the first input of the element OR 19, the output of which is connected to

the second input of the second element AND-NOT 5. The transfer output of the counter 17 is connected through the third inverter 24 to the C-input of the second trigger 12, the S-input of which and the input of the first 5 inverter 22 are connected to the transfer output of the first counter 3, and the output of the first inverter 22 is connected to the second input of the OR-NOT 21 element, the output of which is connected to the second input of the And element 20. The reset inputs of the first 11, second 12, and third 13 triggers are connected to the output of the second inverter 23, the input of which is connected to the bus. Initial setting 10. D-inputs first 11 and second 12 triggers connect 5 cores to the zero potential bus, the second bus. Register register 25 is connected to the recording input of the second register 17 and to the first input of the third AND-NOT 6 element, the output of which is connected to the first input of the fourth AND-NOT 7 element.

The operation of the code-width-pulse converter is illustrated by the diagram in FIG. 1. where a is the output of the 1 pulse generator, b is the output of the first AND-NOT 4 element, c

5 - transfer output of the first counter 3, d - direct output of the first trigger 11, d my output of the second trigger 12, first output bus 14, e - output of the OR-NOT 21 element, g - output of the AND 20 element, s 0 output of the second element AND NOT 5, and is the inverse output of the third trigger 13, and is the transfer output of the second counter 17, k is the second bus. Register write, l is the output of the OR element.

5 Converter code - pulse width signal operates as follows. The device (in the particular case of the microcomputer) generates a signal of the initial installation. Counters 3, 17 and triggers 11,

0 12, 13 are set to O. Through the first AND-NOT 4 element, pulses from the generator 1 are fed to the summing input of the first counter 3. In the second half-cycle of its state 11 ... 1 there will be an active transfer signal (Fig. 2a). The active transfer signal (c) of the first counter 3 sets the first 11 (g) and second 12 (e) triggers to 1. Active logical About the inverse output of the first trigger 11 through the first element AND NOT 4

0 the transfer pulse of the first counter 3 will make it as short as possible. Its duration is equal to the sum of the delays at the first trigger 11, the first AND-NOT 4 element and the first counter 3. The IL-AND-21 element serves as a key,

5 which allows the passage of counting pulses through the element And 20 (e). They will take place at that moment (g), when the first trigger 11 and the inactive transfer signal of the first counter 3 are set to 1. We assume that the recording signals are currently

inactive. Then the counting pulses are fed (h) to the C-input of the third trigger 13. The first positive edge of the signal after the initial installation after the second AND-NOT 5 element sets the third trigger 13 in G, because it is turned on as a divider by two. Active 1 of the third trigger 13 generates a signal. There is no conversion on the second output bus 15. Active О of the inverse output of this trigger 13 generates a signal for setting (first) the first 3 and second 17 counters with the code of the first 2 and second 16 registers, respectively. It should be noted that in order to start the correct conversion of the code into a pulse-width signal, it is necessary to write the conversion code into the first 2 and second 16 registers before the first counter 3 generates a transfer signal. The second positive edge (h) of the signal after this AND-NOT 5 element sets the third trigger 13 to O. The positive edge at the inverse output of the third trigger 13 (s) sets the first trigger 11 to 0. Logical 1 of the inverse output of the first trigger 11 prohibits the passage of counting pulses to the third trigger 13 and allows their passage to the summing inputs of the first 3 and second 17 counters.

The converter operates correctly provided that the code on the input bus 8 is inverse, and in the second register 16 less than in the first register 2. Then, with synchronously working counters in the second counter 17, the transfer pulse (s) appears earlier and resets through the inverter 24 in O second trigger 12 (d).

In the second half-cycle of the state 11 ... 1 of the first counter 3, the transfer signal will again be active. Then the current code-to-pulse-width signal conversion cycle ends and a new tuning of the converter to the codes stored in the first 2 and second 16 registers, which is described above, begins. The presence of the first register 2 allows you to control the conversion period of the pulse width signal. In the second register 16, the actual conversion code is stored.

Now, consider the case when a new conversion code or conversion period is recorded at the time the counters are installed.

Conflict resolution write code in registers or. it was decided to set the counters in the direction of the highest priority of the monitoring device, He is allowed to write to the registers

any moment in time. If at the moment when writing to the registers occurs, the time has come to set the counters with the code of these registers, then while the external

the device does not finish recording, the installation of counters does not occur. This is implemented as follows.

At the outputs of the registers, the information should change according to the positive edge of the signal. Record. Active low level of signals on the first or second bus. Register record through the third AND-NOT 6 element gets to the conflict resolution scheme: fourth 7 and fifth 18

AND-NOT elements, OR element 19. When the signal for setting the counters earlier than the write signal to the registers occurs, the logical O at the output of the OR element 19 (l) is not generated and the installation occurs,

as described above. It should be noted that the duration of the setup signal should be less than the duration of the recording signal. If at the moment when on the first or second bus Register Register is active

signal, the signal for setting the counters arrives, then at the output of the OR element 19 (l) a logical O is formed, which prohibits the passage of pulses to the third trigger 13. Thus, the third trigger

13, which generates a counter setup signal, is not set to 1 until the external device finishes writing to the registers.

At the output of the second trigger, the following time relations are implemented: T (a) 3/2 t (0); T (b) (0) + T (a); T (c) (0) + T (a), where t (0) is the frequency period of generator 1;

N1 - register code 2; N2 is the code of the register 16. The accuracy of the conversion will be the same as in the converter 1. However, if the counters are installed at the moment the code is written into the registers, an additional error is introduced in one conversion cycle, which is determined by the formula f Te / T (with)

where T3 is the time the code was written to the registers;

T (s) is the period of the pulse-width signal.

The inventive converter in comparison with the prototype allows to facilitate

the operation of the control device for managing the conversion code - pulse-width signal, to expand operational capabilities.

Claims (1)

SUMMARY OF THE INVENTION A code converter is a pulse width pulse signal comprising a pulse generator, a first register and a pulse counter, first to fourth NAND elements, first, second and third triggers, the direct output of the second of which is the first output bus. and the direct output of the third trigger is the second output bus, the S-input of the first trigger is connected to the transfer output of the first pulse counter, the first input of the first element is NOT connected to the output of the pulse generator, and the output is to the summing input of the first pulse counter , the information inputs of which are connected to the corresponding outputs of the first register, the information inputs of which are the input code bus, and the write input is the first bus. Register recording, the pulse counter reset input is the bus. Initial installation, characterized in that, in order to expand operational capabilities by increasing the reliability of information when changing the input code, a second register and a pulse counter are introduced into it, the fifth AND-NOT element, the OR, AND, OR-NOT elements, the first, second and third inverters moreover, the information inputs of the second register are the input code bus, and the outputs are connected to the corresponding information inputs of the second pulse counter, the reset input of which is the initial setting bus, and the summing input is connected to the output of the first AND-NOT element, the first input of the AND element is connected to the output of the pulse generator, and the output is connected to the first input of the second AND-NOT element, the output of which is connected to the C-input of the third trigger, the inverse output of which is connected to its D-input and combined with the installation inputs of the first and second pulse counters and with the C-input of the first trigger, inverse the output of which is connected to the second input of the first AND-NOT element, the first input of the OR element and the first input of the OR-NOT element, and the direct output is connected to the first input of the fifth AND-NOT element, the output of which is connected to the first input of the fourth AND-NOT element whose output is is dined with the second input of the fifth AND-NOT element and with the second input of the OR element, the output of which is connected to the second input of the second AND-NOT element, the transfer output of the second pulse counter is connected through the third inverter to the C-input of the second trigger, the S-input of which is connected the transfer output of the first pulse counter and is combined with the input of the first inverter, the output of which is connected to the second input of the OR-NOT element, the output of which is connected to the second input of the AND element, the R-inputs of the first, second and third triggers are combined and connected to the WTO output the first inverter, the input of which is the bus Initial installation, the D-inputs of the first and second flip-flops are the zero potential bus, the input of the second register is the second bus The register is combined with the first input of the third AND-NOT element, the second input of which is combined with the input record of the first AND-NOT, and the output is connected to the second input of the fourth element AND-NOT. ( Csl L1 cЈ B .-i