SU1427571A2 - Frequency digitizer - Google Patents

Abstract

The invention relates to computing and automation, can be used in digital control systems for converting frequency sensor signals into a digital code, and is additional to the basic author. St. No. 970681. The invention improves the speed and expands the range of use of the converter. For this purpose, a converter containing an anti-coincidence unit 1, a crystal oscillator 2, a frequency comparator 3, memory register 4, a reversible counter 5, a code-frequency converter 6, a 7.address register, a multiplexer 8, a pulse shaper 9, a converter 10 are entered period - code and shaper 11 back to code, which allowed quickly obtaining a rough estimate of the measured frequency, followed by eliminating the mismatch between the received and true values of the measured frequency, as well as using the Q converter in multichannel si themes frequency measuring signals in which switching kapov the measured frequency value u varies discontinuously. 1 hp f-ly, 3 ill. S (l

Description

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The invention relates to computing and automation, can be used in digital control systems for converting frequency sensor signals into a digital code, and is additional to the invention in accordance with the authors. St. K 970681.

The purpose of the invention is to increase speed and expand the range of use due to the possibility of preliminary obtaining a rough estimate of the measured frequency.

FIG. 1 shows the structural scheme of the proposed converter; FIG. 2 and 3 are diagrams of a period-code converter and a frequency comparator, respectively.

 The converter (Fig. 1) contains an anti-coincidence unit 1, a crystal oscillator 2, a frequency comparator 3, a memory register 4, a reversible counter 5, a code 6 frequency – frequency converter, an address register 7, a multiplexer 8, a pulse former 9, a converter 10 period - code, the driver 11 of the reverse code, bus 12 Start, address bus 13, input bus 14 and output bus 15.

Period converter - code (Fig. 2) is formed by RS-flip-flop 16, D-flip-flop 17, generator 18, counter 19, element AND 20, element OR 21, delay element 22 and one-shot 23.:

The frequency comparator (Fig. 3) includes two-bit counters 24 and 25, an RS flip-flop 26, one-shot 27 and 28, OR elements 29-31, and delay elements 32 and 33.

The Converter operates as follows.

The whole process of obtaining a frequency code consists of three stages: the stage of quickly obtaining a gross error of the measured frequency, this tracking and the stage of tracking.

At the rough estimation stage, a pulse on bus 12 records the code from bus 13 to register 7 of the address. The address code is fed to the input of the multiplexer 8, which commits in accordance with it one of the input signals from the bus 14 through the pulse shaper 9 to the first input of the anti-coincidence unit 1 and the information input of the converter 10. After the start pulse ends, the converter 10 measures the time interval between the first and second impulse input hour

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tots fjc as follows. The start pulse sets to one three-ger 16 and zeroes counter 19 and flip-flop 17. First pulse f sets to one trigger 17, which resets flip-flop 16 and enables counter 19. The counter 19 fills with pulse f of generator 18. Second pulse fi resets the trigger 17 and prohibits the operation of the counter 19. The signal from the inverse output of the trigger 17 passes through the OR element 21, the delay element 22 and starts the one-shot 23, the pulse of which gates recording to the counter 5. The AND element 20 triggers when the counter 19 is filled, the generator 18 is blocked, and the one-shot 23 is triggered through the OR element 21 and the delay element 22. This is necessary to prevent overflow of the counter 19. Period code N ,. the output of the converter 10 is fed to the shaper 11, which converts the period code N to the coarse frequency evaluation code V}, which is written to the upper bits of the reversible counter 5 by a one-shot pulse 23. The delay element 22 is necessary for the delay of the write pulse at the time of receiving the reverse code in the former 11.

At the tracking stage, the mismatch is eliminated by the true value of the measured frequency and a rough estimate obtained by measuring the period if. Converter 6, which is a trigger frequency divider controlled by counter code 5, generates from frequency fj. -quartz oscillator 2 signal of the compensating frequency f, corresponding to the code in the counter 5 at each moment of time. The frequencies EL and fx are fed to the inputs of block 1, which are assigned to them; they are linked to two synchronizing mismatched sequences — signals from the direct and inverse outputs of the generator 2. From the outputs of block 1, the pulses fi and f go to the summing and subtracting the inputs of the counter 5. In this case, the direction and rate of change of the code in the counter are determined by the frequency difference i) - EK. For example, if f fk, the code in counter 5 increases, and the frequency f will increase until f f. From the exit; Block 1

impulses I K n Hz are also supplied to the inputs of frequency comparator 3, which is intended for fixing the moments of equality of these frequencies. Counter 2A is filled with fiJ pulses. and is reset through the element OR 30 by pulses f. If f, fk ,, then there will be cases when between two pulses f, will be located with at least two pulses, while the output of element 38 will receive a signal confirming the relationship "fc. Counter 25 is similar to counter 24, is filled with pulses f and is reset by pulses,. The signals at the output of the element And 39 confirm: give the ratio f f Trigger 26, set when if f is 1, and when f, f is set to O, changes its state when it changes at the moment of equality of these frequencies. This starts the one-shot 27 or 28, the pulse from the output of which through the element OR 29 rewrites the code of the frequency N / from the counter 5 to the register 4.

At the tracking stage, the code in counter 5 tracks the change in the input frequency fc. The information in register 4 is updated each time frequency comparator 3 is triggered.

The output code Nf of the converter 10 is inversely proportional to the frequency of the input signal:

NL NT f

where is cj

rounding the logo,

fi - frequency generator. The value of f is chosen as follows:

poo

  to

where m is the size of f, pin counter 19J

the minimum value of the measured frequency.

The reverse code shaper 11 can be implemented in the form of a ROM with a capacity of 2 t-bit words. Each possible value of the Nf code is associated with a coarse estimate frequency code N. The ROM coding table can be represented by the formula

Nf

1.1 f

2

NT,

Q g 5

Q

five

The frequency of the crystal oscillator f is chosen equal to the maximum value of the measured frequency f /

Claims (2)

1. Frequency converter - auth. St. No. 970681, characterized in that, in order to improve performance and expand the scope of use due to the possibility of preliminary obtaining a coarse estimate of the measured frequency, a period converter is introduced into it - a code, a reverse code shaper, an address register, a multiplexer and a pulse shaper, and the connected multiplexer and pulse shaper are connected between the input bus of the device and the first input of the anti-coincidence unit, combined with the information input of the period converter. - code, the control input of which, combined Hbtfi with the control input of the address register, is a bus. The converter starts, the output is connected to the record input of the reversible counter, and the group outputs are connected to the corresponding inputs of the return code generator, the outputs of which are connected to the information inputs of the reversible counter The information inputs of the address register are the address bus of the converter, and the outputs are connected to the corresponding control inputs of the multiplexer. 40 five 0 2. The converter according to claim 1, T is characterized in that the frequency comparator contains two single-oscillators, an RS flip-flop, three OR elements, two delay elements and two two-bit counters, the counting inputs of which are respectively the first and second inputs. frequency comparator and combined with the first inputs of the first and second OR elements, respectively, the overflow output of the first two-bit counter is connected to the S input of the RS flip-flop and through the first delay element with the second g input of the second OR element, the overflow output of the second two Razdnogo counter connected to the R-input RS-flip-flop and through the second delay element with the second input of the first elekA27571 j6 OR, the direct and inverse output of which is the output frequency RS-flip-flops are connected to the inputs of the corresponding comparator, and the outputs of the first and first and second single OR elements are connected to the input switches, the outputs of which are connected to the installation in O, respectively respectively with the first and second G1tg, "g, g," inputs of the third element OR exit second and first two-digit meters, G1tg, "g, g," second and first two-digit meters,