SU1216831A1 - Converter of delta-modulated signal to signal with pulse-code modulation - Google Patents

Abstract

The invention relates to computing and can be used in digital information transmission systems. The purpose of the invention is to increase the noise immunity of the conversion by eliminating failures. The device contains a polarity analyzer, the input of which is the device input, control unit, STATUS of NOT, AND-NOT, AND and SH-NE, reversible counter, VI delay triggers, multiplexer, AND AND-NOT elements, frequency divider, connected to the clock bus. The polarity analyzer consists of a trigger and the elements AND, SHSh-NOT and I1Sh. 1 hp f-ly, 4 ill.

Description

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The invention relates to computing technology and can be used in digital information transmission systems.

The purpose of the invention is to increase the noise immunity of the conversion by eliminating failures.

Figure 1 shows the functional diagram of the Converter; in fig. 2 and 3 - functionalities of the polarity analyzer and control unit; figure 4 - timing diagrams of the Converter.

The input 1 of the device is connected to the first input of the polarity analyzer 2, the first output of which is connected to the first input of the control unit 3, the first and second outputs of which are connected to the corresponding inputs of the reversing counter 4. The outputs v of its bits are connected to the inputs of the corresponding h delay delays 5 triggers , the outputs of which are connected: to the information inputs of the multiplex j cop 6 from the second (+1) th f.ooT-, the first information

the input of the multiplexer 6 is connected to the second output of the polarity analyzer 2. The outputs N of the bits of the reversible counter 4 are connected to the corresponding inputs of element 7 AND and element 8 NAND, the outputs of which are connected to the second inputs of the control unit 3, respectively, and polarity analyzer 2. The clock input of the control unit 3 is combined with the clock input of the frequency divider 9 and connected to the clock bus 10. The first and second outputs of the frequency divider are connected respectively to the control input of the multiplexer 6 and the synchronous inputs of the delay 5 triggers. The output of multiplexer 6 is the output of the device.

The polarity analyzer 2 (FIG. 2) consists of a delay trigger 11, element 12 I, element 13 W-NO and element 14 OR, the output of which is first, and the inverse output of trigger 11 is the second output of analyzer 2 polarity, and input and the trigger input synchronization 11 - the first and second inputs of the analyzer 2, respectively. The input of the trigger 11 is connected to the first inputs of elements 12 AND and 13 OR NOT, and its direct output is connected to the second inputs of these elements whose outputs are connected to the input of the elements 14 OR.

8312

The control block 3 of FIG. 3 consists of elements 15 NOT, 16 AND-NOT, 17 AND, and 18 OR-NOT, the Converter of the delta-modulated C DM) signal to

The Pulse Code Modulation (PCM) signal works as follows.

Input 1 converter receives the corresponding analog

a signal and a signal b (Fig. 4) with a DM. Clock pulses B are received over the clock bus 10. At the first and second outputs of analyzer 2, signals 2 and 2 appear.

5 On the first and second outputs of control unit 3, synchronously with clock pulses 6, signals are generated, respectively, direct and reverse counting for a reversible counter 4, on the outputs of which e-I signals appear, the combination of which is a digital combination corresponding to the analog value signal to this

5 point in time.

At the initial moment of time, when a zero combination is present at the outputs of the reversible counter 4, the second input of the analyzer 2

Q polarity from the output of the element 8 AND-NOT- a high logic level, K. Trigger 1} of the analyzer 2 polarity at the same time goes into recording mode and at its direct output a signal a is generated, and on the inverse, which is the second the output of the polarity analyzer, the signal that determines the sign of the PCM code word. If at the direct output of the trigger i1

.Q is a high logic level, then the signal 7. at the first output of the analyzer 2 polarity completely repeats the signal S. If, on the direct output of trigger 11, a low logic level

e ven (such a situation arises when a zero pulse train arrives at the first input of the polarity analyzer 2 with a high logic level at the second input

, - polarity analyzer), then signal 2. is inverse with respect to signal B. At the second output of the analyzer 2 polarity, there is a high logic level 55 9

Since in the general case the sampling rates of the DM and PCM signals are different, to form the output

PCM signal applied 5 delay trigger. To translate the parallel code, which is formed on the direct outputs of the trigger 5 delays, into the serial used multiplexer 6, providing a serial connection of the P triggers 5 to the output of the device.

If a reverse counter is present at the outputs, 4 combinations 1 1 1 ... 1, i.e. limit value, element 7 And generates a high logic level, which, entering the second input of control unit 3, prohibits the further increase in the readings of counter 4 before the negative pulse train enters control unit 3. This prevents the overload of the counter 4 and the inverter from malfunctioning.

The frequency divider 9 provides at the first output signals with a frequency of t4 +1 times higher than the second. In this case, a serial PCM signal is generated at the output of the multiplexer 6.

Claims (3)

Invention Formula . A delta-modulated signal into a pulse-modulated signal containing a reversible counter, a control unit and delay triggers, the inputs of which are connected to the outputs of the corresponding bits of the reversible counter, the first and second inputs of which are connected to the corresponding outputs of the control unit, This is due to the fact that, in order to increase the noise immunity of the conversion by eliminating failures, a frequency divider, an AND element, an NAND element, a multiplexer and a polarity analyzer, are introduced into it which is an input device, a second input connected to the output of AND-NO element, first analyzer output polarity connected to the first input of the control unit, and the second output to a first multiplexer input information, other information inputs of which are connected to the outputs of the corresponding 8314 auix delay triggers, the multiplexer output is the device output, and the control input is connected to the first output of the frequency divider, the second output of which is connected to the synchronization inputs of the delay triggers, the input of the frequency divider is connected to the clock input of the control unit and connected to clock bus, the second input of the control unit is connected to the output of the AND element, whose inputs are combined with the corresponding inputs of the NAND element and connected to the outputs of corresponding bits of the reversible counter. 2. The converter according to claim 1, T is characterized in that the polarity analyzer consists of a delay trigger, an AND element, an OR element, and an OR-NOT element, the first input of which is combined with the first input of the AND element and the delay trigger input and the first entry polarity gate, the delay trigger trigger input is the second polarity analyzer input, the forward delay trigger output is connected to the second inputs of the AND elements and W-NO, whose outputs are connected to the corresponding inputs of the OR element, the output of which is the output of the polarity analyzer, and the inverse output of the delay trigger is the second output of the polarity analyzer. 3. The converter according to claim 1, T is characterized in that the control unit contains AND-NOT, AND, OR-NOT and NOT elements whose input is combined with the first input of the AND-NO element and connected to the first input of the control unit, and the output of the element is NOT connected to the first input of the element I, the second input of which is combined is not with the second input of the element is NOT and connected to the clock input, the output of the element AND-NOT connected to the first input of the element OR NOT, the second input of which is connected to the second input the control unit, and the outputs of the NL-HE and I elements are respectively the first and second outputs of the control unit. Wus one " -1 IB re but I 1 n and t Compiled by O. Revinsky Editor S. Patrusheva Tehred T. Dubinchak Proofreader M. Demchik Order 1005/61. Circulation 818 VNIIPI State Committee, USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Branch P1Sh Patent, Uzhgorod, Proektnash street, 4 gp g fig a Subscription