RU1793452C - Device for information transmission - Google Patents

Abstract

The invention relates to telecommunications and can be used in information transmission and storage systems. The aim of the invention is to expand the scope of the device by transmitting pulse-width signals of various kinds. The device for transmitting information includes a clock, a first counter and a first AND element, the output of which is connected to the clock input of the switch, a second counter, the output of which is the control output of the device, two OR elements, the second control input connected to the second input a switch, the third and fourth OR elements, the control input of the clock being the trigger input of the device, and the second trigger. The device is characterized in that an HE element, a delay element, AND elements, a counter and a decoder are inserted into it, the information inputs of which are connected to the outputs of the first counter, while the input of the element is NOT combined with the first inputs of the fifth and sixth AND elements and is the control the input of the device, the output of the first element AND is connected to the clock input of the fourth counter, the control input of which and the start input of the switch are the start input. devices, the output of the fourth counter is connected to the second inputs of the switch ate, the second AND element, the third OR element, the output of which is connected to the second input of the third AND element, the outputs of the second, and the fifth OR element are connected to the second and third inputs of the second OR element, whose output is connected to the input of the third counter, the output of the second counter connected to the third input of the switch, the fourth input of which is combined with the second inputs of the fourth and fifth elements AND and connected to the output of the subtracting counter. 4 ill. (L o w

Description

The device relates to telecommunications and can be used in transmission and storage of information.

The aim of the invention is to expand the scope of the device by transmitting pulse-width signals of various kinds.

In FIG. 1 is a structural diagram of an apparatus for transmitting information; eeyore

FIG. 2 is a structural diagram of a switch; in FIG. 3 - structural diagram of the counter; NC FIG. 4 is a structural diagram of a decoder.

The device for transmitting information (Fig. 1) contains a clock generator 1, a first AND element 2, a second counter 3, a switch 4, a subtracting counter 5, a first counter b, a first trigger 7, a fourth OR element 8. a third counter

9. the element is NOT 10, the first and third elements of the IL. AND 11 and 12, the second trigger 13, the second and sixth elements of the OR 14 and 15, the fifth element of the OR 16, the decoder 17, the delay element 18, the fourth counter 19, the fifth, second, third, sixth and fourth elements AND 20-24, trigger input 25, control input 26, information input 27, first control output 28, information output 29, second control output 30, output 31 of counter 19, output 32 of the element NOT

10. output 33 of the subtracting counter 5.

The switch 4 (Fig. 2) contains the first and second elements OR 34 and 35, three elements And 36-38, two triggers 39,40:

Counters 3, 9, and 19 contain (Fig. 3) an And 41 element, a counter 42, a decoder 43, and a pulse shaper 44 .; ; .., 4 C

The decoder .17 contains (Fig. 4) the element NOT 45, two elements AND 46 and 47 ..,. The device operates in two modes,

In the first mode, in each time frame of a fixed duration, the device performs an oreobbryvanie to determine the number of code-pulse subunits of the information block, the IB pulse-delayed, (PWM) signals and the serial transmission of these signals to the communication channel. In this case, the neighboring W and M signals inside each frame (block) are separated from one another by alternating the amplitudes (zero and one) of these signals | 6b, and the sequence of PWM signals between frames is separated by time intervals (we will call in further this type of SHNM adaptive),

In the second mode, the subunits are encoded into normal signals; one-sided PWM: the duration of the conversion interval of each subunit is constant, the duration of the interval of potential is ripo proportional to the code value of this subunit, the duration of the conversion of the subunit is calculated in such a way that corresponds to the maximum value of the input signal code. In this case, each subunit is converted into a time interval proportional to the value of the subunit (single signal), and a pause - its duration is equal to the difference between the interval proportional to the value of the subunit and a fixed interval allocated for each subunit. This is an ordinary, one-sided SCHM (hereinafter, we will call it OSHIM as opposed to the previously described ASHIM).

The pulse generator generates pulses by which the conversion is performed - recounting to form input pulses of auxiliary duration of the required duration, depending on

values of the output code of the corresponding subunit.

Counter 3 has a conversion factor m, for each output pulse in any operating mode, a constant component of the duration.

Switch 4 determines the operation mode of the device — by the signals it sets the time intervals for the arrival of pulses to the counters 3 and 5.

A 5-subtracting counter determines the width of a pulse-width modulated pulse proportional to the input code.

Counter 6 sets a fixed duration for the conversion of the entire block of information (depending on the operating mode).

Counter 9 counts the number of sub-blocks of kbB data in a common block. The decoder 17 determines the processing time of the entire data block depending on the mode and controls the counter 6.

The counter 19 determines the duration of the fixed processing time interval of the data subunit in the ORR mode.

The device operates as follows. -; : - :: - v; -. ..- V .. ..:. ACHIM signal generation mode. At the same time, a high potential is established at input 26, which is maintained during the entire interval of the device’s operating time in this mode. This signal opens the elements And 20 and 23 and closes the elements And 21, 22, 24, and also controls the switching of blocks 4 and 17. At the initial moment, the code of the first information sub-block is supplied to the inputs 27, and the input 25 is short

positive Start signal. In this case, a signal is generated from the output of the element

OR 14 and through the elements OR 11 and AND 23

changes the state of the trigger 13, the positive front of the signal from the output of the OR element 14 is written to the counter 5, the code of the first sub-block from the inputs 27, the signal from the output of the OR element 14 is fed to the counting input of the counter 9, however, a high potential at the input 25 during the start pulse keeps counter 9 in Zero State until the end of the pulse

trigger, In block 4, the trigger signal triggers 39 and 40 are set through the elements OR 34 and 35 in the single and zero state, respectively, opening the element And 37, the trigger signal starts the generator 1.

counter 6 is reset via the OR element 15, trigger state 7 is set to 6 through the AND AND 8 element, opening the And 2 element, the counters 3 and 19 are reset. Pulses from the generator 1 are transmitted through the And 2 element to the counter 19 and to the input

switch 4, from the output of which (element And 37), are counted into counter 3, counting m is a constant component of the output pulse used to synchronize the receiver. After the counter 3 is overflowed, the pulse from its output sets the trigger 40 of block 4 to the single state and switches the block 4 to transmit pulses from the generator 1 to the counter 5. The same output pulse 28 gives the request to the external output device for the next data subunit. The switch 4 switches the pulses from the generator T to the subtracting input of the counter 5 through the And 38 element, the zero Reset pulse of the counter 5 comes through a time interval proportional to the code of the subunit, and the output 33 again switches the block 4 to the switching of pulses to the counter 3, through the open element And 20 and OR 14 writes the code of the new subunit to counter 5, increments the contents of counter 9, through the elements of OR 11, AND 23 changes the state of the trigger 13 and the output signal 29. This happens for all subunits. After the last subunit, counter 9 overflows and generates a signal that resets trigger 7 and closes AND 2 for clock pulses, further conversion of subunits is suspended. At the output 29, a separation interval is formed, the end time of which is determined by the decoder 17, the pulse from it through the OR element 15 resets the counter b, from the output. OR element 16, an impulse is generated for setting the external device to a mode setting request for converting the next data block. Moreover, the user at a given time can change the operating mode of the device by changing the potential at the input 26 and applying a pulse to the input 25, the interval is determined by the delay element 18.

ERROR mode. In this mode, the nodes of the device, as described above, are reset. Differences: trigger 13 with the Start signal through the elements OR 12 and AND 22 is set to one state, the elements AND 21, 22, 24 are opened, the channel of the decoder 17 is switched, the principle of control of the 4. unit is changed..:.

Similarly, in the OSHIM mode, the counter 3 is recounted first, then the data sub-block code is recounted by the counter 5. After the counter 5 is overflowed, the trigger 40 switches to the zero state, opening the And 37 element, however, with the same signal, the And 36 element is open

trigger 39 is cleared, locking elements AND 37 and 38 for the period of pause formation. In this mode, the signal from the output of the counter 5 enters the trigger 13 through the elements And 24

5 and nullifies it at the end of the formation of this subunit and the transition to the formation of a pause. Counter 19 has a conversion factor constant for each pulse for each data subunit. After the trigger 13 is switched to zero, the device expects the counter 19 to operate, which (occurrence of the signal at the output 31) sets the trigger 39 of block 4 to the single state, opening for the passage of pulses to

5 counter 3, through the elements AND 21 and OR 14 increments the counter 9, writes the code of the new data sub-block to the counter 5, sets the trigger 13 again to the single state through the elements OR and 12 and 22, starts

0 conversion of the next data subunit.

Likewise, the end of the mode after the counter 9 is overflowed; the device at output 30 requires the determination of a new transmission mode for the next data block.

To control the duration of the intervals separately in each mode, for example, c0 of output 32 (dotted line, Fig. 1), the frequency of generator 1 can be adjusted.

Counters 3, 9, 19 can be performed similarly (Fig. 3). An external reset signal is applied to the input of the OR element. Counter,

5, by counting the input pulses, it reaches a state in which the decoder 43 is activated, made, for example, in the form of a coincidence circuit, according to which the counter is zeroed, and by the shaper 44

0 pulse of the required duration, sufficient to trigger subsequent nodes. but not allowing the presence of a constant potential at the output when the meter is connected to subsequent nodes and their execution on

5 potential principle

The counter 5 can be performed similarly with the addition of circuits for parallel recording of the input code.

In the decoder 17 (Fig. 4) to the inputs of the groups

0 elements 46 and 47 are connected in the required combination of direct and inverse outputs of counter 6. In ASCHM mode, element I 47 works, in OCHIM mode, element I 46. Thus, the claimed device

5 expands the scope due to the fact that in addition to the ASCHM mode at the user's choice, it is possible to switch to the OCHIM mode, i.e., two modes of operation with simple switching are allowed.

Claims (1)

The claims A device for transmitting information, comprising a clock generator, the output of which is connected to the clock inputs of the first counter and the first element AND, the output of which is connected to the clock input of a switch, the first output of which is connected to the input of the second counter, the output of which is the control output of the device, a subtracting counter, the information inputs of which are information inputs of the device, the first control input and the first input of the first OR element are connected to the output of the second OR element, the second the control input is connected to the second output by the switches, the first inputs of the second, third and fourth OR elements, the control inputs of the clock generator of the second and third counters are the device start input, the output of the fourth OR element is connected to the first input of the first trigger, the second input which is connected to the output of the third counter, the output of the first trigger is connected to the control input of the first AND element, the second trigger, OR elements, and so on, in order to expand the scope of application devices by transmitting pulse-width signals of various types, the element is NOT entered, the delay element, the elements AND, the counter and decoder, the information inputs of which are connected to the outputs of the first counter, control input is connected to the first inputs of the second, third and fourth elements / and the first the input of the switch and is connected to the output of the element NOT, the input of which is combined with the first inputs of the fifth and sixth elements And is the control input of the device, the output of the first AND element is connected to the clock input of the fourth counter, the control input of which and the start input of the switch are the start input of the device, the outputs of the decoder through the fifth element OR connected in series and the delay element are connected to the second inputs of the fourth and first elements OR, the output of the latter is connected to the second input of the sixth element AND, the output of which and the outputs of the third and fourth elements AND are connected to the inputs of the second trigger, the output of which is the output device, the decoder outputs are connected to a first input of the sixth OR element, the second input of which is combined with the control input of the clock generator and with the control input of the fourth counter, the output is connected to the input of the first counter, the fourth counter output is connected to the second inputs of the switch, the second AND element, the third OR element, the output of which is connected to the second input of the third AND element, the outputs of the second and fifth OR elements are connected to the second and third inputs of the second OR element, the output of which is connected to the input the third counter, the output of the second counter is connected to the third input of the switch, the fourth input to the input is combined with the second inputs of the fourth and fifth elements AND and connected to the output of the subtracting counter, izh1 Fig.Z Fi g 4