SU1467782A1 - Device for transmitting binary signals - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to provide the transmission of asynchronous signals. The device contains a source of I digital signals, a source of 2 sync signals, delay blocks 3 and 4, counting triggers 5 and 9, an ELIMINATOR OR 6, a majority block 7, a frequency divider 8 and a matching unit Y. The goal is achieved by forcibly dropping into About the splitter 8. This ensures the required synchronism of the operation of the counting trigger 9 and the receipt of input data, and ultimately the ability to work with asynchronous input information. 2 Il.

Description

4 О5 1 00 to

15

one

The invention relates to telecommunications and can be used in discrete information transmission systems.

The purpose of the invention is the transmission of asynchronous signals.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - timing diagrams for the operation of the device.

The device contains a source of 1 digital signals, a source of 2 sync signals, U blocks 3 and 4 delays, a second counting trigger 5, an EXCLUSIVE OR 6 element, a majority block 7, a frequency divider 8, the first counting trigger 9, a matching block 10.

The device operation is as follows.

The digital binary signal (Fig. 2a), delayed in block 3 (Fig. 2c), is fed to the input of element 6 and, after a delay in block 4 (Fig. 2g), to another input of element 6.20

Block 4 and the EXCLUSIVE OR b element form a scheme for detecting changes in the input signal, the output of which (Fig. 2e) produces short pulses whose leading edges coincide with the moments of changing the signal level at the output of block 3, and the duration is determined by the delay of block 4.

The input information signal directly from the source 1 is fed to the R-bypass of the counting flip-flop 5, to the C-input of which a signal is fed from the source 2 (Fig. 2b). This signal is a pulse sequence whose frequency is twice the rate at which information is received from source 1, where n, 2 ... (a case is presented for greater visibility in Figure 2). The clock phase is in no way connected with the moments of changing the values of the information signal, i.e., these signals are asynchronous. As the source 2, both a built-in and an external clock generator can be used. Turning on the counting trigger 5 defines its operation as a controlled clock frequency divider into two, the low level of the information signal allows division, and the high level blocks it, dropping it into “About trigger 5 (Fig. 2e).

The joint inclusion of the source 2, block 3, the counting trigger 5 and the majority block 7 provides the formation

at the output of the majority block 7 a pulse sequence is formed, the law of which frequency change can be represented by the expression

. FJf (l + D),

where F is the frequency of the generated sequence; fan is the frequency of the original clock signal;

(О - at logical zero at the output of the block 3 1 - at logical unit at the output

block 3.

Obviously, by dividing the signal at the output of the majority block 7 by the device, a pulse sequence corresponding to the bi-pulse representation of the original information signal from source 1 can be obtained. This is ensured by the sequential switching on of the divider 8 and the counting trigger 9, which together create the desired division ratio.

25

thirty

The delay of the original information signal in block 3 causes divider 8 to constantly be late with a change in the frequency of the output signal. As can be seen from FIG. 2c (first stage divider) and FIG. 2i (the second stage of the divider), changes in the frequency of the generated pulse sequences occur with a delay in relation to the original information signal by the delay time of block 3 (in this case, equal to the period of the original clock signal). This delay leads to the fact that the phase of the pulse sequence at the output of the counting flip-flop 9 does not change irregularly, but after a certain intermediate value (Fig. 2 / s, the locked pulses). The signal received at the output of the counting trigger 9 corresponds to the bi-pulse representation of the original information signal, with the main phase change ensuring the specified reliability of the transmission.

As can be seen from FIG. 2e, the pulses generated at the output of the EXCLUSIVE OR 6 element and arriving at the R-input of the divider 8 do not affect its operation when they are present at the moments of cyclic zeroing of the divider 8 bits, i.e., when the divider 8 cycle of operation coincides with the phase of input information.

45

at the output of the majority block 7 pulse- Otherwise occurs when they are out of sync

variable frequency variable sequences (Fig. 2 g). The phase and duration of the generated pulses coincides with the phase and duration of the sync signal from source 2. The frequency of the generated sequence is equal to the frequency of the sync signal at intervals when the signal level at the output of block 3 corresponds to a logical one and is half as long at a logical zero. In this way.

(the initial part of the diagram of Fig. 2g), when divisor 8 is forcibly reset to "O", which ensures the required synchronism of the counter and incoming data, and ultimately 55 the ability to work with asynchronous input information.

The matching unit 10 provides for the conversion of electrical parameters

at the output of the majority block 7 a pulse sequence is formed, the law of which frequency change can be represented by the expression

. FJf (l + D),

where F is the frequency of the generated sequence; fan is the frequency of the original clock signal;

(О - at logical zero at the output of the block 3 1 - at logical unit at the output

block 3.

Obviously, by dividing the signal at the output of the majority block 7 by the device, a pulse sequence corresponding to the bi-pulse representation of the original information signal from source 1 can be obtained. This is ensured by the sequential switching on of the divider 8 and the counting trigger 9, which together create the desired division ratio.

with

five

0

The delay of the original information signal in block 3 causes divider 8 to constantly be late with a change in the frequency of the output signal. As can be seen from FIG. 2c (first stage divider) and FIG. 2i (the second stage of the divider), the changes in the frequency of the generated pulse sequences occur with a delay in relation to the original information signal by the delay time of block 3 (in this case, equal to the period of the original clock signal). This delay leads to the fact that the phase of the pulse sequence at the output of the counting flip-flop 9 does not change irregularly, but after a certain intermediate value (Fig. 2 / s, the locked pulses). The signal received at the output of the counting trigger 9 corresponds to the bi-pulse representation of the original information signal, with the main phase change ensuring the specified reliability of the transmission.

As can be seen from FIG. 2e, the pulses generated at the output of the EXCLUSIVE OR 6 element and arriving at the R-input of the divider 8 do not affect its operation when they are present at the moments of cyclic zeroing of the divider 8 bits, i.e., when the divider 8 cycle of operation coincides with the phase of input information.

five

 Otherwise happens when they are out of sync

Otherwise happens when they are out of sync

(the initial part of the diagram of Fig. 2g), when divider 8 is forcibly reset to "O", which ensures the required synchronism of the counter and incoming data, and ultimately the ability to work with asynchronous input information.

The matching unit 10 converts the electrical parameters of the transmitted signal to a form acceptable for transmission to the communication channel.

Claims (1)

Invention Formula A binary signal transmission device containing a digital signal source, a clock source, the first, second delay blocks, the first counting trigger, the output of which is connected to the input of the matching unit, whose output is the output of the device, characterized in that, in order to transmit asynchronous signals, a second counting trigger, an EXCLUSIVE OR element and a frequency divider, the output of the digital signal source being connected through the first and second delay units connected in series to the first input of the AND element KEY OR, the second input of which is connected to the output of the first delay unit and the first input of the majority unit, the second input of which is connected to the output of the clock source and the C input of the second counting trigger, the R input, and the output of which are connected respectively to the output of the digital source signals, and the third input of the majority block, the output of the EXCLUSIVE OR element is connected to the R-input of the frequency divider, the C-input of which is connected to the output of the majority block, and the output to the input of the first counting trigger. 3 rin rbJTJiJiJirmJiimju K | J J li LJJ LjJSS FIG. 2