SU1001460A1 - Binary code-to-time interval converter - Google Patents

Description

The invention relates to a pulse technique and can be used in devices for converting and encoding information.

A known converter of a binary code into a time interval containing a reference frequency generator, two triggers, a counter, three coincidence elements, a comparison unit and a delay element (£ 1).

The known device uses a counter with bitwise transfer, and the output of the pulse at the end of the time interval occurs at (M + 1) clock after preliminary preparation of the circuit according to the Mth pulse of the clock frequency.

A disadvantage of the known device is the low accuracy of the converter, since it is determined by the period of the clock frequency of the reference generator, which, when the duty cycle of the frequency of the reference generator is 2, cannot be selected in the converter less than ΚΪ, · where 'C is the switching delay time of one counter element; K is the number of counter triggers.

The purpose of the invention is to increase the accuracy of conversion without presenting more stringent requirements for the speed of individual elements of the counter and thereby without reducing the reliability of the counter.

This goal is achieved by the fact that in the device containing the first matching element, the first input of which is connected to the output of the reference frequency generator jq, and the second input is connected to the output of the first trigger, as well as the counter, the comparison unit, the second matching element, the second trigger, connected in series, a third matching element and a delay element 15, the output of which is connected to the reset inputs of both triggers, additionally. ' a circular register is kept, the input of which is connected to the output of the first coincidence element, and the output is connected to the counter input of the counter and to the second inputs of the second and third coincidence element.

Figure 1 presents the structural diagram of the proposed Converter; 25 in FIG. 2 is a timing chart explaining its operation.

The converter consists of a trigger Ϊ, a coincidence element 2, a ring register 3, a frequency generator 4, a counter 5, a comparison unit 6, a coincidence element 7, a trigger 8, a coincidence element 9, and a delay element 10.

The converter operates as follows.

The beginning of the formation of the time interval is preceded by a record in a certain category of the ring register of a unit by submitting a binary code that does not correspond to the category of the register and into certain bits of the counter of the code, the inverse of the code being converted. The moment of arrival of pulses to a single input of trigger 1 corresponds to the beginning of a time interval. (Fig. 2 _f <y). In this case, trigger 1 is set to} 5 into a single state '(Fig. 2, ^ 2 and pulses from the reference frequency generator 4 (Fig. 2, d) are input to the ring register 3. Fill pulses from the output of the ring register ( figure 2, d) are received at the input of the counter 5. After passing the Mth pulse from the ring register, all the triggers of the counter 5 are set to state 1, while the comparison unit 6 generates a signal (figure 2, e), which is input to the input of element 7 The pulses from the ring register 3 are applied to the second input of the coincidence element 7. At the moment of coincidence of these signals, a pulse appears from the output of element 7 (FIG. 2, g), trigger 8 is set to a single state (FIG. 2, h) and allows the passage of the next (M + 1) pulse from the ring to the output of the device through element 9 register as a pulse at the end of the time interval (Fig. 2, i). The same pulse arrives through the delay element 10 ^ (Fig. 2, k) at the input of the installation at 0 triggers 1 and 8, which, when locked, prohibit the passage of all subsequent after ( M + 1) th pulses from the ring register to the input of the counter 5 and the input of element 9. For echeniya opening member 9 overlap only on transit time (m + 1) -th pulse with a ring register, a signal that sets flip-flop 8 into the state 'Ί, begins on the falling edge of the M-th pulse;

Since from the last trigger of the ring register 3, pulses with a frequency N times smaller than the pulse frequency from the generator 4 of the reference frequency (Fig. 2a) are received at counter 5, then the inverse binary code of not the number of GTs is written to counter 5, where r - = 1, 2, 3 ..., depending on the size of the time interval, and the inverse binary code of the number VT / N. In this case, the discrete appearance of the enabling signal at the output of block 6 will be equal to NT and, in order to keep the discrete equal to T, i.e. thus, the first input of the counter 5 appears such a period of time to form time intervals through the period of repetition of pulses of the reference generator, the unit in the ring register is recorded in a well-defined trigger depending on the interval, the pulse is transmitted through nothing, which is an addition to the time interval, determined by an integer number of pulse repetition periods from the ring register, gives the necessary value of the time interval.

Thus, the use of a ring register makes it possible to reduce the period of the reference frequency generator without increasing the performance requirements for the elements of the ring register and counter. Due to the fact that the conversion error is determined by the period of this generator, the proposed device provides an increase in conversion accuracy. The speed of the ring register is determined only by the speed (delay of one element, while the period of the output pulse sequence increases by N times compared to the period of the reference frequency generator, where N is the number of register elements. Thus, the total signal propagation time in the counter should not exceed N't ', which is N times greater than. in the main device. Therefore, as a counter in the proposed device, it is possible to use a simpler, and therefore more reliable in operation In this case, the delay time of an individual counter element should not exceed Νΐ / Κ, where K is the number of elements in the counter. If рав = K is fulfilled, the period of the generator of the reference frequency is reduced by L times, and thereby increase by K | times the conversion accuracy at the same speed of the elements of the proposed device, as in the known device.

Claims (1)

comparison, match 7, trigger 8, match 9, and delay 10. The Converter operates as follows. The beginning of the formation of a temporary and. The terraces are preceded by writing to a certain bit of a ring register unit by submitting a binary code that does not correspond to the bits of the register and to certain bits of the counter to the inverse of the code to be converted. The moment of arrival of pulses to a single input of trigger 1 corresponds to the beginning of the time interval (Fig. 2 (DG. In this case, the trigger 1 is set to one state of FIG. 2, -) and the generator 4 of the reference frequency arrives at the input of the ring register 3 (Fig. 2 g) Filling pulses from the output of the annular register (Fig. 2, d are fed to the input of counter 5. After the passage of the M-th pulse from the ring register, all the triggers of counter 5 are set to state 1, with this comparison block forming the signal of figure 2, e}, the input element 7 The second input of the coincidence element 7 is pulsed from the ring register 3. At the moment of coincidence of these signals, the pulse from the output of the element 7 is received (Fig2, x}, the trigger 8 is set to one state (Fig. 2, g) and allows the output of the device to pass through element 9 of coincidence of the next (m + 1) pulse from the ring register as a pulse to the end of the time interval (figure 2, and the same pulse goes through an element 10 h delay (figure 2, k) to the installation inputs in About Triggers 1 and 8, which are locked, prohibit the passage all subsequent (m + 1) -g pulses from the ring register to the input of counter 5 and the input of element 9. To ensure that element 9 coincides with opening for the transit time of the (M + 1) -th pulse from the ring register, generating a trigger 8 to state 1, starts on the trailing edge of the M th pulse. Since the last trigger of the ring register 3, the counter 5 receives pulses with a frequency N times less than the frequency of the pulses from the generator 4 of the reference frequency (FIG. 2, y), then in counter 5 is written reverse binary the code is not numbers GT, where r is 1, 2, 3 ..., depending on the size of the time interval, but the reverse binary code of the number GT / N. In this case, the discrete occurrence of the decisive signal at the output of block b will be equal to NT and, in order to keep the discrete equal to T, i.e. to be able to form time intervals after the pulse period of the reference generator, the unit in the ring register is written to a well-defined trigger depending on the size of the converted interval. Thus, the first pulse at the input of the counter 5 appears after such a period of time that the addition to the time interval determined by an integer number of periods of pulses from the ring register gives the necessary Eremnogo interval. Thus, the use of a ring register can reduce the period of the reference frequency generator without increasing the speed requirements for ring register elements and the counter. Due to the fact that the conversion error is determined by the period of this generator, the proposed device provides an increase in the conversion accuracy. The speed of the ring register is determined only by the speed (delay T;} of one element, the period of the output pulse sequence is increased by a factor of 1x compared to the period of the reference frequency generator, where .N is the number of register elements. Thus, the total propagation time of the signal in the counter should not exceed Nt, which is N times more than in the main device. Consequently, as a counter in the proposed device, it is possible to use more simple, and therefore more reliable At the same time, the delay time of a separate counter element should not exceed Nt / K, where K is the number of elements in the counter. When N K is equal, a reduction in L times the reference frequency generator, and thus an increase in Vl, is achieved. differences in the conversion with the same speed of the elements of the proposed device as in the known device. Invention A binary code converter is a time interval containing the first element, a match, the first input of which oedinen yield oscillator reference frequency, and a second input coupled to an output of the first flip-flop and counter connected in series, the comparator, the second element of coincidence, the second flip-flop, a third sovpaeni element and a delay element whose output is connected to a reset input both triggers, differing in the fact that, in order to increase the accuracy of the conversion, an annular register is added to it, the input of which is connected to the output of the first matching element, and the output is connected to the counting input of the counter and to the second inputs of the second and third element of the match. Sources, information taken into account in the examination, 51. USSR author's certificate No. 445144, cl. H 03 K 13/04, 1972. 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