SU839065A1 - Device for computing the difference of pulse trains - Google Patents

Description

The invention relates to computer technology and is intended for use in equipment for obtaining various clock signals.

The pulse repetition rate divider with a variable division coefficient is known, which contains a pulse counter with a controlled conversion factor of £ 1 ^.

The disadvantage of this device is its complexity.

The closest in technical essence to the invention is a recounting device with a controlled conversion factor, containing sequentially connected counting triggers, the inverse outputs of which are connected to the inputs of the matching elements, the second inputs of which are connected to the control inputs, and the inverse outputs are connected to the inputs of the AND-NOT element, the output which is connected to the first input of the auxiliary trigger, the second input of which is connected to the inputs of the device, binary counter and auxiliary element AND NOT, and the inverse output auxiliary trigger - with the input of the output AND-NOT element, the second input of which is connected to the output of the auxiliary AND-NOT element, and the output - with the reset input of counting triggers £ 2j.

The disadvantage of this device is its low reliability.

The purpose of the invention is to increase the reliability.

This goal is achieved by the fact that in the pulse frequency divider with a variable division ratio, containing a pulse counter, the inverse outputs of which are connected to the first inputs of the matching elements, the second inputs of which are connected to the control buses, and the inverse outputs to the inputs of the first AND-NOT element, the output of which is connected to the first input of the trigger, the second input of which is connected to the counting input of counts 839065 4 pulses, the second AND-NOT element, the output of which is connected to the first input of the third AND-NOT element, the output of which connected to the input of setting to zero imuplsov counter, a first input of the second AND-NO element is connected to the inverted output of the flip-flop, the second input - to the third input of the third flip-flop and the output of AND-NO element, a second input coupled to a second input of the flip-flop.

Figure 1 presents the structural diagram of the device; figure 2 - timing diagrams explaining his work.

The device contains a counter 1 im- 15 pulses, elements 2 matches, trigger 3, elements NAND 4-6, output 7, control 8 and input 9 bus.

The device operates as follows. 20

In the initial state, control buses 8 are set, for example, binary code 00 10, there are no input pulses on input bus 9, the outputs of element 5 and one of 25 elements 2 are low, and the outputs of other elements are high. The counter 1 starts to count the input pulses received through the input bus 9 until the code 30 matches the code on the control buses 8. When the codes coincide, high levels appear on all outputs of elements 2, and therefore, 35 elements exit 4 - low. At this moment, an input pulse (high level) is present on input bus 9. At the end of the input pulse, i.e. by the presence of a low level at the first 40 and second input of trigger 3, the latter is triggered and a low level appears at its inverse output, which passes through element 5 at a high level to the input of element 6, thereby preparing ⁴⁵ to issue the next input pulse to the output of the device. When a low level appears at the output of the device, this level in the feedback circuit maintains the state of element 5, resets trigger 3 (a high level appears at the inverse output) and counter 1. At the end of the output pulse, the device returns to its initial state.

Thus, in comparison with the known device, the proposed frequency divider has higher reliability and, in addition, provides output signals during the action of the input pulse and has a lower delay between the input and output pulses.

Claims (2)

The invention relates to computing and is intended for use in the equipment of a dp for receiving various clock signals. The izvesten frequency divider of the pulse or pulse with a variable division factor, containing an impulse counter with a controlled conversion factor UlJ The disadvantage of this device is its complexity. The closest in technical essence to the invention is a scaling device with a controlled scaling factor, containing sequentially connected counting triggers, the inverse outputs of which are connected to the element inputs, the second inputs of which are connected to the control inputs, and the inverse outputs - to the inputs of the AND- element. NOT, the output of which is connected to the first input of the auxiliary trigger, the second input of which is connected to the inputs of the device, the binary counter and the auxiliary element NAND, and the inverse output to the auxiliary trigger is with the input of the output element IS-NOT, the second input of which is connected to the output of the auxiliary element IS-NOT, and the output is connected to the reset input of the counting trigger 2. The disadvantage of this device is low reliability. The purpose of the invention is to increase the reliability of work. This goal is achieved by the fact that, in the pulse frequency divider with a variable division factor, contains a pulse counter, the inverse outputs of which are connected to the first inputs of the coincidence elements, the second inputs of which are connected to the control buses, and the inverse outputs to the inputs of the first AND element the output of which is connected to the first input of the trigger, the second input of which is connected to the c4eTHONry input of the pulse counter, the second AND-NOT element, the output of which is connected to the first input of the third AND-NOT element, the output of which is under for prison setting to zero entry imushtsov counter, a first input of the second AND-NO element is connected to the inverted output of the flip-flop, the second input - to the third input of the third flip-flop and the output of AND-NO element, a second input coupled to a second input of the flip-flop. Figure 1 shows the structural diagram of the device; 2 shows timing diagrams explaining its operation. The device includes a pulse counter 1, coincidence elements 2, trigger 3, AND-HE elements 4-6, output 7, control 8 and input 9 buses. The device works in the following way. In the initial state, on the control buses, there is 8 3-dan — for example, binary code 0010, on the input bus 9 there are no input pulses, on the outputs of element 5 and one of elements 2 low levels, and on the outputs of the remaining elements high levels. Counter 1 starts counting incoming pulses through the input bus 9 until the code is established in it, which coincides with the code on the control buses 8. When the codes on all outputs of elements 2 coincide, high levels appear and, consequently, the output of element 4 is low. At this point, the input bus 9 is present input pulse (high level). At the end of the input pulse, i.e., the presence of a low level at the first and second inputs of trigger 3, the latter is triggered and at its inverse output a low level appears that passes through element 5 with a high level at the input of element 6, thus preparing outputting the next input pulse to the device output. When a low level appears at the output of the device, this level of the feedback circuit maintains the state of element 5, resets trigger 3 (the inverse output appears high) and counter 1. At the end of the output pulse, the device returns to its initial state. Thus, in comparison with the known device, the proposed frequency divider has a higher reliability and, moreover, provides higher output signals during the action of the input pulse and has a smaller delay between the input and output pulses. The invention The pulse frequency divider with a variable division factor, containing a pulse counter, the inverse outputs of which are connected to the first inputs of the coincidence elements, the second inputs of which are connected to the control buses, and the inverse outputs to the inputs of the first element Y-NOT, whose output connected to the first input of the trigger, the second input of which is connected to the counting input of the pulse counter, the second element IS-NOT, the output of which is connected to the first input of the third element IS-NOT whose output is connected to the pulse counter is set to zero, in order to increase reliability of operation, the first input of the second AND-NE element is connected to the inverse trigger output, the second input — to the third trigger input and the third IS-output output, the second input of which Connected to the second trigger input. Sources of information taken into account during the examination 1. USSR authorial reference number 517165, cl. H 03 K 23/24, 14.10.74. 2. Instruments and equipment of experiment No. 5, 1977, p.89.