SU1656685A2 - Serial-to-parallel converter - Google Patents

Abstract

The invention relates to computing and can be used in data transmission systems over digital channels to convert a serial code into a parallel one and is an improvement of the basic invention according to the author. St. No. 1262732. The invention allows to ensure the operability of the converter in the absence of an input signal, thus achieving expansion of the field of application of the converter. The converter contains a shift register 1, a buffer register 2, a control block 3, a pause allocation block 4, an exchange controller 5 and an OR element 6. The exchange controller 5 contains AND elements, an interval counter, an NOT element and a divisor counter. 1 h. apt., Zil.

Description

FI.1

The invention relates to computing, can be used in data transmission systems over digital channels and is complementary to the author. St. No. 1262732.

The aim of the invention is to expand the field of application of the converter by maintaining its operability in the absence of an input signal.

FIG. 1 shows a functional block diagram of a converter; Fig 2 is a functional circuit of the exchange controller; in fig. 3 - timing diagrams explaining the operation of the exchange controller.

The converter includes a shift register 1, a buffer register 2, a control block 3, a pause allocation block 4, an exchange controller 5, and an OR element 6.

FIG. 1, positions 7–9 denote, respectively, the synchronization input, the code synchronization input and the information input of the converter, and the positions 10 and 11 denote the information output and the control output of the converter, respectively.

The exchange controller 5 contains the first 12 and second 13 elements AND, the interval counter 14, the element NOT 15, the counter divider 16.

FIG. 3 corresponding indices denote the following signals: a - the signal at the counting input of the counter-divider 16; b - the signal at the output of the counter-divider 16; in - the signal at the output of the element And 12; g - signal at the output of the interval 14 counter; d - the signal at the output of the element And 13.

The pause allocation unit 4 determines the transmission boundary of two adjacent words by comparing the length of the pause between two adjacent code clock pulses with a period of reference clock pulses (input 7) following a frequency close to the code clock frequency. With a significant difference in the duration of the pause between the clock pulses of the code and the period of the reference clock pulses, which corresponds to a pause in the transmission of information, a pause pulse is generated at the output of the pause allocation unit 4. The pause pulse overwrites information from the shift register 1 into the buffer register 2.

As the sequential code arrives at input 9 and the code clock at input 8, information is received in shift register 1. The shift register 1 shift is chosen more than two bits than the received code width, and the code value of the additional bits determines the correct operation of the converter. These two bits of the code, together with the pause pulse, arrive at

a control unit 3, at the first output of which a pulse of the initial setting of the shift register 1 is formed, and at the second - a signal for the end of the conversion. 5If the number of sync pulses between two pause pulses is nominal (n N), then in additional oasds n + 1 and n + 2 of shift register 1, code 10 is written, according to which a conversion signal is generated from the pause pulse, confirming the correctness of the conversion and the possibility use of information.

5If the number of sync pulses of the code is less than the nominal (n N), then in additional bits the code 00 is written, according to which the signal of the end of the transformation is not generated. In both cases, a pulse of the initial setup of the shift register 1 is generated by the pause pulse signal, and thus the shift register 1 is prepared to receive a new word.

If the number of sync pulses of the code is more than the nominal (), then as soon as the code 01 or 11 appears in the extra bits, an early formation of the initial setup of the shift register 1 is performed.

0 Thus, the control unit 3, depending on the code in the additional bits of register 1, either generates the initial impulse formation, or the sequential generation of the conversion end and initial installation pulses, and for three types of the control length of the received word between two pause pulses (less than, equal to or greater than nominal)

0 in the additional bits of register 1, the code 00 or 01 corresponds to this case and according to these codes and a pause pulse, either an initial setup pulse (code 00) or a recording pulse to buffer register 2 and a signal to the Conversion end are formed followed by the initial setup pulse. (code 01) or code 10 (1 G), which is used to form the initial pulse

0 installation.

Thus, with a word length greater than the nominal one, the situation after zeroing inside the cycle (before the pause pulse) is reduced to the situation of receiving a code with a width less than nominal. The first input of the exchange controller 5 receives the clock pulses from the input 7, the frequency of which is reduced by the counter-divider 16 to a frequency determined by the required speed of information input to an external device,

and through the element 12 is fed to the counting input of the interval counter 14. If the end of the conversion from the control unit 3 does not pass to the second input of the exchange controller 5, which indicates the absence of sync pulses at the input 8 of the converter, the interval counter 14 counts the signal log, 1, and, accordingly, the signal log.O at the output of the element is NOT 15, which allow or prohibit the passage of impulses through the elements 12 and 13, respectively. In the presence of pulses at the second input of the exchange controller 5, the counter 14 is periodically zeroed, without having time to check to see the log. 1 at its output. The pulses passing through the element OR 6 are determined by the frequency of arrival of the information words (signals End of conversion). When pulses disappear at a sounding time greater than the analysis interval, determined by the frequency of input pulses at input 7 and the conversion factors of counters 16 and 14, the frequency of the pulses passing through the element OR 6 is determined with the frequency of the input pulses and conversion factor of counter 16 .

Thus, in the presence of a received code, the received information is stored in the buffer register 2, and the output is carried out synchronously with the end of the reception of the code. In the absence of a received code in the analysis interval after its termination, periodic resetting of buffer register 2 occurs, and the output is carried out synchronously with zeroing pulses.

Claims (2)

1. Serial code to parallel converter for aut. St. N; 1262732. characterized in that, in order to expand the scope of the converter by maintaining its operability in the absence of an input signal, an OR element and an exchange controller are added to the converter, the output of which is connected to the zeroing input of the buffer register and the first input of the OR element, the first input exchange controller is combined with the first input of the pause allocation unit, the second inputs of the exchange controller and the OR element are combined and connected to the second output of the control unit, the output of the OR element is prav- .l yuschim output transducer. 2. The converter according to claim 1. about tl and h a and y with the fact that the exchange controller is made on the elements AND, the interval counter, the element NOT and the counter-divider, the output of which is connected to the first inputs of the first and second elements AND , the interval counter vygood is connected directly by the second input of the second element AND and through the element NOT to the second input of the first element I. whose output is connected to the counter input of the interval counter, the counter input of the counter divider and the zero input of the interval counter are respectively the first and second inputs controller, an output of second AND gate is vyho controller's house. 9and d.1 a a iiMMimilMMiiiMMiniinii i i i iIlIL I g i i iIL Jil 0te.J