SU1730728A1 - Device for sequentially correcting errors - Google Patents

Abstract

The invention relates to the transmission of data and can be used for sequential correction of errors such as offset. The aim of the invention is to expand the scope by correcting errors in codes with two zero protective bits. The device contains from first to third triggers 1.1-1.3, counter 2, element AND 3, first to third elements OR 4-6, and element 7 of the delay with links. 1 il. YO VJ SO O VI ihO 00

Description

The invention relates to the transmission of data and can be used for sequential correction of errors such as offset.

The aim of the invention is to expand the field of application by correcting errors in codes with two zero protective bits.

The drawing shows a diagram of a device for successive error correction.

The device contains the first to the third triggers 1.1-1.3, respectively, counter 2, element I 3, first to third elements OR 4-6, respectively, delay element 7, information input 8 of the device, output 9 of the device, clock input 10 of the device, input 11 reset device.

At the receiver of the data transmission system, the decision to receive O or 1 is made at the time of the arrival of the clock. With various noises and the effect of communication channel parameters, bias errors occur (left or right). In order to correct such errors, the source code is proposed: a (o) a (1) a (2) ... a (m-1) to convert to 0 a (0) 00 a (1) 00 a (2) 00 .. . 00 a (m-1) 0, (1) where between the code bits are placed two protective zero bits, and also one protective bit is placed on the boundaries of the package. Thus, the code sequence corresponding to the initial one is of length n 3M.

The signal E (S), which corrects errors such as level shifting left-right, is formed according to the algorithm

E (S) a (S-1) + a (S + 1), (S 3i-2, 1-1,2, ... n / 3) (2)

Triggers 1.1-1.3 are designed to memorize the next three-bit portion of the code, the average bit of which is informational, and the rest are redundant.

Counter 2 (conversion factor 2) sets the device operation mode. After recording the next portion of the code, it sends a signal to the third and fourth inputs of the And 3 element.

About O Clock Sync 1 About 1

counter sync pulse 2

1 o

Oh oh

Sync pulse 3

Element And 3

 otkoyt

The initial state of the counter 2 - 0.0

Element And 3 checks the bits of the triggers 1.1 and 1.3 after the third clock pulse, and element OR 6 - the arrival of the error signal of the triggers triggers 1.1 and 1.3 at the first input of the element 3. The delay element 7 delays the clock pulse to ensure that the And 3 element operates after the trigger counter 2.

The device works as follows

Suppose that through input 8, the code combination 010 is written to the triggers 1.1–1.3, we synchronize clock pulses, the counter 2 is set to

state 00, the element OR 6 is not triggered (as the combination is not distorted) and when the clock pulse is received from the delay element 7, the element And 3 does not issue a code correction signal,

In case of distortion of the combination

T 1.1

five

Orj1 Oh o

Reset

T 1.2 1 0 1 O

Installation

T1.3 O

O 0

About 1

ABOUT

Correction

Displacement

left right

Element OR 6

generates an error signal and after the third clock pulse, which sets counter 2 to the state 0,0, the element 3 triggers, which sets the triggers 1.1 and 1.3 to the zero state, and the trigger 1. 2 to the state one.

Thus, the device corrects all left-right offset errors according to formula (2) in code patterns of the form (1), thereby increasing the noise immunity of receiving information as a result of the more complex structure of the code pattern,

Claims (1)

Claims An apparatus for successive error correction comprising first to third triggers, a counter, an AND element, first to third OR elements, wherein the output of the AND element is connected to the first inputs of the first and second OR elements, the outputs of the first and third triggers are connected respectively to the first and second inputs of the third element OR, the output of which is connected to the first input of the element AND, the clock input and the reset input of the device are connected respectively to the counting input and the reset input of the counter, the output of the third trigger is the output of the device, different the fact that, in order to expand the scope by correcting errors in codes with two zero protective bits, it contains a delay element, and the clock input of the device is connected to the inputs enable the recording of the first and third triggers, with the second input of the second OR element and the input of the delay element, the output of which is connected to the second input of the AND element whose output is connected to the installation inputs 0 in About the first and third triggers, the inverted outputs of the bits of the counter output are connected respectively to the third and fourth inputs of the element And, the information input of the device is connected to the information input of the first trigger, the output of which is connected to the second input of the first element OR, the output of which and the output of the second element OR connected, respectively, to the information input and the write enable input of the second trigger, the output of which is connected to the information input of the third trigger.