SU1520668A1 - Device for converting serial code to parallel code - Google Patents

Abstract

The invention relates to computing, in particular, to information converters, and can be used in information transmission systems by a serial code with subsequent conversion to parallel one. The invention eliminates unauthorized interruptions in the reception of information, thereby improving the noise immunity of the device. A device for converting a serial code into a parallel one contains registers 1 and 2 of shift, a generator of 3 clock pulses and OR-NOT elements 4 and 5. 1 Il.

Description

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Iss

The invention relates to computing technology and can be used in information transmission systems by a serial code with its subsequent conversion into a parallel code.

The aim of the invention is to improve the noise immunity of the device.

The drawing shows a structural diagram of the device.

A device for converting a serial code into a parallel one contains the first 1 and second 2 shift patterns, a generator of 3 clock pulses, the first, 4 and second 5 ILI NOT elements and has the first 6 and second 7 outputs, start input 8 and information input 9.

The device is working. following up.

Input 8 receives a signal that writes 1 to the first bit of shift register 1, and to the remaining bits, O, writes information S to shift register 2, and outputs 6 and 7 sets state 10 and starts generator 3 clock pulses, the output pulses from which V through the element OR NOT 5 arrive at the clock input of the shift register 1. As you arrive; code pulses of an arbitrary sequence at input 9, register 1 receives incoming information. In the case of receiving the expected n bits of a sequential code without a fault in (n + 1) -m. (The last but one) and (n + 2) (the last), bits of register 1, code 10 is written, and the information inputs of register 2 are set signals With the arrival of the next signal at input 8, the levels of C1; 1 signals, located at the inputs of register 2, are copied to the outputs, and at outputs 6 and 7, code 00 appears, indicating that the information has been correctly received.

If 33 of the shift process I is preliminarily recorded in the first digit of the 1-shift register, in the latter an excess shift type fails, then 1 moves from the (rt + l) -ro bit of the shift register 1 to the (n + 2) -th bit e. At the same time signal 1 ,. appeared in the (n + 2) -th bit, through the element SH1I-NO 5 prohibits the further passage of clock pulses to the register I of the move. State 1 in

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The (n + 2) th bit at the same time indicates that an extra shift has failed, and the clocking of clock pulses allows you to save this information, and it does not matter how many clock cycles there is an extra shift. At the inputs of the shift register 2, signals 01 are set, which, with the arrival of a signal at input 8, are written into shift register 2 and arrive at outputs 6 and 7. Code 01 signals an extra shift failure. At the next setting of the shift register 1 to the reception of information, the lock of the generator 3 is automatically removed when the SRI of the (n + 2) -th bit of the shift register 1 is cleared. In the case of a type failure, the missing shift by one or more clock cycles of the reference frequency 1, previously recorded in the first bit of the shift register 1, does not appear at the outputs of the (n + O-th and (n + 2) -th) bits, and at the inputs shift register 2 is set to code 10, which, by a signal from input 8, is written to shift register 2, and code 10 is set to outputs 6 and 7, signaling the failure of the missing shift.

Claims (1)

Invention Formula A device for converting a serial code into a parallel j containing the first shift register, whose information input is the information input of the device, the second shift register, the first and second outputs of which are the device of the same name, and the clock generator, the input of which is combined with the input of the installation of the first shift register, with the input of the recording of the second shift register and is the input of the recording device, so that, in order to increase the noise immunity of the device, It introduced the elements SHS-NOT the output of the first element OR-NOT connected to the first informational input. The second shift register, the output of the clock generator is connected to the first input of the second element. And the ShH-NOT, the output of which is connected to the clock input of the first shift register and which is connected to the first input of the first element of the IPI-NOT, the output of the last bit of the first shift register is connected to 515206686 the second inputs of the first and second ration inputs of the second register of OR-NOT elements and with the second information shift.