SU1660193A1

SU1660193A1 - Block synchronizer

Info

Publication number: SU1660193A1
Application number: SU894636354A
Authority: SU
Inventors: Сергей Леонидович Макаренко
Original assignee: Предприятие П/Я М-5209
Priority date: 1989-01-12
Filing date: 1989-01-12
Publication date: 1991-06-30

Abstract

Изобретение относитс к технике электрической св зи и может быть использовано дл блочной синхронизации в цифровых системах передачи информации. Цель изобретени - повышение помехоустойчивости. Устройство содержит счетчик 1 текущей цифровой суммы, последовательные регистры 2 и 3, параллельный регистр 4, дешифратор 5 запрещенных комбинаций, счетчик-накопитель 6, решающий блок 7, блок 8 формировани импульсов разрешени и элемент ИЛИ 9. Повышение помехоустойчивости достигаетс за счет использовани сигнала с выхода младшего разр да счетчика 1 текущей цифровой суммы в качестве сигнала окончани блоков информации, при этом фазировка счетчика 1 не зависит от ошибок в канале св зи. 4 ил.The invention relates to electrical communication technology and can be used for block synchronization in digital information transmission systems. The purpose of the invention is to improve noise immunity. The device contains the current digital sum counter 1, the successive registers 2 and 3, the parallel register 4, the decoder 5 prohibited combinations, the counter-drive 6, the decisive block 7, the resolution impulse generation unit 8 and the OR element 9. The increase in noise immunity is achieved by using the signal from the output of the low bit of counter 1 of the current digital sum as the signal of the end of the blocks of information, while the phasing of counter 1 does not depend on errors in the communication channel. 4 il.

Description

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Claims

Claim

A block synchronization device containing a counter of the current digital sum, a counter-accumulator, a decision block, a parallel register, the first and second sequential registers, the information and clock inputs of which are combined with the corresponding two information and clock inputs of the counter of the current 5 digital sum, and the inputs of the device, and the outputs are connected to the information inputs of the parallel register, and the outputs of the counter-drive are connected to the information inputs of the decisive unit, about 10 l available in that, in order to increase I am noise immunity, it contains a forbidden combinations decoder, a resolution pulse generation block, and an OR element whose output is connected to the 15th input of the counter-zeroing device, whose information inputs are connected to the outputs of the forbidden combinations decoder, whose inputs are connected to the outputs of the parallel register, and the first? 0 the input of the OR element is connected to the output of the decisive block, the input of the counter installation of the current digital sum, the output of which is connected to the clock input of the parallel register, the first and second ' 5, the outputs of the resolution pulse generation block are connected respectively to the control input of the decision block and the second input of the OR element,

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