SU1018251A1 - Three-valued or gate - Google Patents

Abstract

TRIPLE ELEMENG OF CONNECTION, containing two four-input ternary logic elements, the first and second input buses, which are respectively connected to the first and second inputs of the first four-input ternary logic element, the output of which is connected to the first input of the second four-input three-way logic element, the output of which is connected to the output bus, and with the fact that, in order to simplify, the first input bus is connected to the third input of the first and to the third input of the second four-input cable logical elements, and the second input bus, respectively, with their fourth inputs.

Description

The invention relates to a pulse technique and can be used in the design of logical nodes of information systems on ternary logic elements with pulse inputs and outputs. A three-digit dislocation element is known that contains a transistor, diodes, resistors, and ferrite cores. The disadvantages of this device are the complexity of the device and the heterogeneity of the element base used. Also known is a three-digit disjunction element, containing three four-input and one two-headed ternary logic elements C2. A disadvantage of the prior art is complexity. The aim of the invention is to simplify the device. The goal is achieved by the fact that in a three-digit element there is a disjunction containing two four-input ternary logic elements, the first and second input buses, which are respectively connected to the first and second inputs of the first four-input three-way logic element, the output of which is connected to the first input of the second four-input three-way logic element whose output is connected to the output bus, the first input bus is connected to the third input of the first and to the third input of the second four-input ternary logical their elements, and a second input bus is - according to their fourth inputs. FIG. 1 shows a diagram of a three-digit disjunction element; in fig. 2 - timing diagrams of the three-digit disjunction element. The three-digit disjunction element contains two four-input ternary logic elements 1 and 2, the first and second input buses 3 and k, which are respectively connected to the first and second inputs 5 and 6 of the first four-input ternary logic element t, the output 7 of which is connected to the first input 8 of the second four-input ternary logic element .2, the output of which is connected to the output bus 9, the first input bus. 3 is connected to the TC-GT input of the first and to the third input 11 of the second four-input ternary logic elements 1 and 2, and the second input bus A, respectively, with their: Fourth inputs 12 and 13. FIG. 2 the following notation is adopted: the diagrams Нр 15 and 16 are the forms of voltages of the first, second and third phases of the device power supply, respectively; diagrams 17 and 18 are input bus signals 3 and diagrams 19 and 20 are signals at the outputs of elements 1 and 2, the following symbols being used. write +1, - “- write -1, h“ ir read O,, JL read +1, --ly read -1. The code combinations in ternary form are fed to the input buses 3 and devices, with a signal at the output of element 2 that uniquely corresponds to the input signal combination. When the ternary code is applied to the input buses 3 and 4 of the device 41, it is represented by a signal of positive polarity, -1 is a signal of negative polarity, and O is no signal. The device’s clock power supply system is three-phase, with the input signal combination on buses 3 and elements 1 and 2 arriving through three phases (one clock cycle) of transmitting information along circuit elements (Fig. 2, diagrams 1 A, 15 and 16. The clock pulse of the second phase is read information from element 1, and the third phase from element 2. Pulses arrive at the buses 3 and during the clock pulse of the first phase .The three-digit information from buses 3 and 4 is converted into information on the three-digit output of element 2 according to Table 1. blitz 1

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Four-input ternary logos according to table. 2 Slano into the browsing elements perform ternary subscriptions of the inputs for the element) j.

table 2

The functionality of the circuit of disjunction 9 in accordance with the input combination (+ 1i, n) is carried out as follows (timing diagrams in figure 2,

By the clock pulse of the first phase of the first clock cycle, according to the operation logic of the element recorded in block 2, a positive signal from the input bus 3 is transmitted to the first input 5 of element 1 and written +1, during the clock pulse of the second phase it is read + 1.c element 1 is transmitted At the first input 8 of element 2, and recorded with a third phase clock pulse, the output of element 2 is a positive signal corresponding to the input combination (+1.0) and transmitted to the output bus 9.

Similarly, -In accordance with figure 1 and 2 and table. 1, transform a) 1 and subsequent input combinations.

The use of a three-digit disjunction element provides, in comparison with the known device, a simplification of the device, an increase in reliability, and a decrease in manufacturability. JoKTL f TL Takgs JffKrji- / rr / Takgb || Shch1D111R tiiHH "AI I 1 m" irfr 1 I .--

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Claims (1)

A THREE-VALUED DISJUNCTION ELEMENT, containing two four-input ternary logic elements, the first and second input buses, which are respectively connected to the first and second inputs of the first four-input ternary logic element ^{: an} output whose output is connected to the first input of the second four-input ternary logic element, the output of which is connected to the output bus, with the fact that, in order to simplify, the first input bus is connected to the third input of the first and to the third input of the second four-input ternary logical elements, and the second input bus, respectively, with their fourth inputs.