SU1119167A1 - Decoder - Google Patents

Abstract

A DE-EMFRATOR containing seven ternary logic elements, the first folding inputs of the first, second and fourth ternary logic elements are connected to the first input bus, the first subtractive input of the first three-fold logic element is connected to the second input width, and the first subtractive inputs of the second and fourth ternary logic elements are connected with the third input bus, characterized in that, in order to improve speed, the eighth ternary logic element is introduced, the first subtractive input of which is connected to About the second subtracting input of the fourth and first subtracting inputs of the sixth and seventh ternary logic elements and the clock bus, its second subtracting input with the first subtracting inputs of the third and fifth, - the second subtracting input. the house of the seventh and the first folding input of the sixth ternary logic elements and the first input bus, its first folding input with the second subtractive inputs of the second, fifth and sixth, the first folding inputs of the third and seventh and the second folding input of the fourth ternary logic elements and the second input bus, and its second folding input - with the second subtractive inputs of the first and third, the first folding input of the fifth and second folding inputs of the sixth and seventh ternary logical elements ntov and third input bus.

Description

The invention relates to pulse engineering and automation and can be used in the construction of devices for processing discrete information. The ternary decoder code 1.0, 1 is known in binary code on ternary elements, which converts the input information for two phases of the clock power Cl 3. The disadvantage of this decoder is low speed. The closest to the proposed is a decoder containing seven ternary logical elements 1 @, the first folding inputs of the first, second and fourth ternary logical elements are connected to the first inlet bus, the first subtracting input of the first ternary logical sensor is connected to the second input terminal, and the first subtracting the inputs of the second and fourth ternary logic elements are connected to the third input bus and the outputs of the first, second and fourth ternary logic elements are connected to the corresponding inputs for Basic C23. However, this descrambler also has low speed, since the code conversion takes place in two phases of clock power. The chain of the invention is an increase in speed. This goal is achieved by the fact that a decoder containing seven threefold logic elements, the first folding inputs of the first, second and fourth threefold logic elements are connected to the first input bus, first subtracted (the input of the first threefold logic element is connected to the second input bus, and the first subtracting inputs of the second and the fourth ternary logic elements are connected to the third input bus, the eighth ternary logic element is introduced, the first subtraction of which input is connected to the second subtractive input the fourth fourth and the first subtracting inputs of the sixth and seventh ternary logic elements and the clock bus, its second subtracting input - with the first subtractive inputs of the third and fifth, the second subtractive input of the seventh and the first square of the sixth ternary, logical elements and the first input bus , its first folding input with the second subtraction inputs of the second, fifth and sixth, the first folding inputs of the third and seventh and the second folding input of the fourth ternary logic elements and the second input hydrochloric bus, and the second folding its input - with the second vychitayushlmi 1 and the first and third inputs, the first input of the folding of the fifth and sixth inputs of the second folding and seventh ternary logic elements and a third input bus. FIG. 1 shows a decoder block diagram; in fig. 2 shows timing charts with symbols. The decoder contains ternary logic elements 1-8, input buses (inputs), clock bus 12, output buses (outputs) 13-20. Each ternary logic element performs ternary operations described in Table. 1. These operations form a functionally complete system of logical functions and can be implemented on the basis of ferrite logic elements on magnetic logic cells. The first input bus 9 is connected to the first folding inputs of elements 1,2,4 and 6, the first subtractive inputs of elements 3 and 5 and the second subtractive inputs of elements 7 and 8. The second input bus 10 is connected to the first subtractive input of element 1, the second subtractive inputs of elements 2, 5, and 6, the first folding inputs of elements 3, 7, and 8 and the second folding input of element 4. The third input bus 11 is connected to the first subtracting 4 inputs of elements 2 and 4, the second subtracting 1 SC input of elements 1 and 3, the first folding of the input of element 5 and second and folding inputs of elements 6, 7, and 8. Clock bus 12 is connected to the first high, reading inputs of elements 6, 7, and 8 and the second subtractive input of element 4. The outputs of elements 1 - 8. are connected respectively to the output tires 13 - 20. FIG. 2 are 21,22 and 23 time — pulse diagrams of the first, second and third phases of the clock power supply, respectively; 24, 25 and 26 time-pulse diagrams, respectively, of signals on buses 9, 10 and 11; / 27-34 - time-pulse diagrams of signals, respectively, at the output 5G of ternary logic elements 1-8, the decoder works as follows. The input busbars 9-11 of the decoder are supplied with code combinations in binary form (via bus 9 with a weight of 2, bus 10-2, bus 11-2), while on one of the output buses 13-20 of the decoder (at the outputs of 1-8, a positive polarity signal appears, unambiguously corresponding to the input signal combination. When giving a binary code to bus 9, 1 is represented by a positive polarity signal, and O is a negative polarity signal. When applying a binary code to buses 10 and 11 - 1 is represented by a positive polar signal, and O is not a signal. The decoder clock power supply is three-phase, while the input code combination of signals to buses 9-11 elements 1-8 enters through three phases (one clock cycle) of information transmission over the device elements (4 mg. The second-phase clock pulse reads information from elements 1- 8. | Signals arrive at tires 9–12 elements 1–8 during the clock of the first phase, and clock signals 12 receive signals with a clock frequency and in the absence of information on the first and second folding and second subtractive inputs of elements 6–8 and first, second warehouse amplification of the first subtracting input of element A, they will be signal generators is in negative pi NOSTA. The information from the two-digit inputs 9-11 is converted into information on the two-digit outputs 13-20 according to the table. 2, and is represented by a positive polarity signal, and O is a negative polarity signal in the absence of a signal. The operation of the decoder in accordance with the input combination (000) is carried out as follows (Fig. 1 and 2). By the clock pulse of the first phase of the first clock cycle, according to the operation logic of the element (Table 1), a negative signal with an input bus 9 at a switch is transmitted to the first folding input of element 1 and the second subtractive input of element 8 and is written into them +1 and -1, respectively, and a positive signal from the clock bus 12 is transmitted to the second subtractive input of element 4 and the first subtractive inputs of elements 6-8 and is written to them -1. The clock pulse of the second phase positive signal from the output of element 1 is transmitted to the output bus 13, forming the signal uniquely corresponding to the input combination (000). Similarly, in accordance with Figures 1 and 2 (Table 2), the transformations of subsequent input combinations occur. The use of the proposed decoder provides a twofold increase in speed, since the conversion of input information in this decoder occurs in one phase of clock power, and in the prototype in two phases of clock power. It also enables the use of this decoder in systems with two-phase clock power. Table 1

oh oh oh oh oh

± 1 o

t1 o

.jt About

{one

+ (-)

Output

th + (-)

+ (-) + (-)

eleven

f

n

J

Th

a

Toktt 1 bct2 Izk Tzk / pi Tbkt5 Toktb Tayu7 Taktv

Impulses mpexipa HOW ucrAot HUKa power Record 1-1 Record -1 CifumbiSaHue

Cycling -1

With about

.g

Claims (1)

A DECODER containing seven ternary gates, the first folding inputs of the first, second, and fourth ternary gates are connected to the first input bus, the first subtracting input of the first ternary logic element is connected to the second input bus, and the first subtracting inputs of the second and fourth ternary logic elements are connected to the third input bus, characterized in that, in order to improve performance, introduced the eighth ternary logic element, the first subtracting input of which is connected to the second the subtracting input of the fourth and first subtracting inputs of the sixth and seventh ternary logic elements and a clock bus, its second subtracting input with the first subtracting inputs of the third and fifth, the second subtracting input of the seventh and the first folding input of the sixth ternary logic elements and the first input bus, its first folding input - with the second subtracting inputs of the second, fifth and sixth, the first folding inputs of the third and seventh and the second folding input of the fourth ternary logic elements and a second input bus, and its second folding input - with the second subtracting inputs of the first and third, the first folding input of the fifth and second folding inputs of the sixth and seventh ternary logic elements and the third input bus. »1119167