SU1272495A1 - Switching device - Google Patents

Abstract

The invention relates to a pulse technique and can be used as a digital information switch. The purpose of the invention is to increase speed by inserting a fifth ferrite logic element 5 and a clock bus 9 into the switch. The drawing also shows ferrite logic elements 1-4, buses: control 6 , nulling 7, informational 8, output 10. The use of this switch on ferrite logic elements provides, as compared with the prototype, a speed increase of 1.5 times, so how the information in this switch is converted in two phases of the clock supply. 2 nl. 2 tab.

Description

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The invention relates to a pulse technique and can be used as a switch of digital information.

The aim of the invention is to increase speed.

FIG. 1 shows a switch circuit on ferrite logic elements; in fig. 2 is a timing diagram of its operation with the legend. .

The switch contains five ferrite logic elements 1-5, control, nulling, information, clocking and output buses 6-10, respectively. Bus 6 is connected according to the first inputs of the first pairs of elements and 3 and to the second input of the first pair of element 2. Bus 7 is connected according to the second input of the first pair of element 1. Bus 8 is connected according to the first input of the first pair of element 2 and to the first inputs of the third pairs of elements 3 and 5. Bus 9 is connected according to the first input of the second pair of element 2 and to the second input of the first pair of element 3 the output of element 1 is connected according to the first input of the first pair of element 4. The output of element 2 is connected counter to the first inputs of the first and second pairs element 4, output element 3 connected according to the second inputs of the first and second pairs of output member 5. The member 4 is connected according to the first inputs of the second pairs of elements 1 and 3 and to the second input of the second pair of element 2, output member 5 is connected to the bus 10.

The clock supply system of the switch is three-phase, with each next pulse arriving at the information bus 8 through three phases (one clock) or after a period of time that is a multiple of three phases. The pulses are fed to tines 6–9 during the clock, the pulse of the first phase. Pulse pulses of the second and third phases are read pulsed information from elements 1-3 and 4 and 5, respectively.

FIG. 2, timing diagrams of 11-13 clock pulses of the first to third phases, respectively, timing diagrams of 14-16 pulses on tires 6-8, respectively, timing diagrams of 17-21 recording and reading pulses on elements 1-5, respectively. The point above the x-axis on diagrams 17-21 corresponds to

recording information on the first input of a ferrite logic element (remagnetization of the first ferrite information core of any pair), a point under the x-axis corresponds to recording information on the second input of the ferrite logic element (remagnetization of the second ferrite information core of any pair), and the polarity of the output pulse when reading from the ferrite the logic element is determined by the retail points above and below the x-axis. If the number of points above the x-axis is greater (less) than that under the x-axis, a pulse of positive (negative) polarity, if there are the same number (or none at all), there is no pulse.

The control windings of the first (second) ferrite information cores of the first to third pairs are the first (second) inputs of the first. third pairs of ferrite logic element. The output of the ferrite logic element can be connected according (counter) to the input of another ferrite logic element relative to the clock bus connected to the power source, then + (-) sign is placed on this input of the element with its symbol. A ferrite logic element can have 2n inputs, where n 1-4 (n is the number of pairs of ferrite information cores in a ferrite logic element).

The ferrite logic element performs the ternary operations described by tab. i.

The first (second) inputs of the first, second and third pairs of a ferrite logic element are equivalent to each other in terms of reading from it a pulse of positive (negative) polarity.

At the inputs and at the output of the ferrite logic element there can be two-pole pulses: negative (-1), positive (+1) and zero (O, i.e., there is no pulse).

An information bus is fed to the information bus, and from the output bus 10 it is removed, respectively, an impulse format in binary (+1, 0) and ternary (+1, O, -I) pop-up systems. The clocking bus 9 receives positive polarity pulses with a frequency of the same power supply.

When a pulse of positive polarity arrives at the bus 6, it is memorized on elements 1 and 4, i.e. the state of the switch from zero to single. Then a positive polarity impulse arriving at the bus 8 is converted on elements 3 and 5 and a negative polarity impulse is removed from the bus 10. When a positive polarity impulse arrives at the bus 7 on the element 1, the switch is reset, i.e. the state of the switch from one goes to zero. Then a positive polarity impulse arriving at the bus 8 is also removed from the bus 10 by a positive polarity impulse,

In tab. 2 shows the switch operation in seven examples (for seven cycles).

The clock pulse of the first phase of the first cycle, according to the logic of the element recorded in the table. 1, the pulse of positive polarity goes through the information bus 8 to the first input of the first pair of element 2, the first inputs of the third pair of elements 3 and 5, as well as through the clocking bus 9 to the second input of the first pair of element 3 and the first input of the second pair of element 2; The second-phase clock pulse from element 2 reads a pulse of positive polarity that does not record information in element 5; A third phase clock pulse from the cell 5 reads a positive polarity pulse, which is transmitted to the output bus 10. Thus, a positive polarity pulse applied to the bus 8 is also transmitted by a positive polarity pulse to the bus 10 without changing the internal state of the switch.

Similarly, in accordance with FIGS. 1 and 2, the switch operation is performed in examples 2-7 of the table. 2,

The use of the proposed switch on ferrite logic elements provides, as compared with the known, an increase in the speed of operation by 1.5 times, since the information in the proposed switch is transformed in two phases

clock feed, and in the well-known three-phase clock feed.

Table I

table 2

Claims (1)

Invention Formula The switch, which contains the control, zeroed the CPU, information and output buses, and four ferrites 1 x 1. logic element, ferrite cores made on pairs, input windings of which are connected to the corresponding inputs of a ferrite logic element, output windings are connected counter-series and connected to its output, control bus and information busses are connected according to the first input of the first pair of the first, second input the first pair of the first and the first input of the first pair of the second ferrite logic elements, respectively, the output of the first. ferrite logic element is connected according to ne the first input of the first pair of the third ferrite logic element, the output of which is connected according to the first input of the second pair of the first ferrite logic element, the output of the second ferrite element is connected counter to the first input of the first pair of the fourth ferrite logic element, the output of which is connected to an output bus, characterized in that , in order to improve speed, introduced five ferrite logic element and clock bus, the first input of the second pair of the second and the second input, the first pair of five ferrite logic elements are connected according to the clock bus, the second input of the first pair of the second and the first input of the first pair of fifth ferrite logic elements are connected according to the control bus, the output of the second ferrite logic element is connected opposite to the first input of the second pair of the fourth ferrite logic element, the output of the third ferrite logic element is connected with It is clear to the second input of the second pair of the second and to the first input of the second pair of fifth ferrite logic elements, the output of the fifth ferrite logic element is connected according to the second inputs of the first and second pairs of the fourth ferrite logic element, and the first inputs of the third pairs of the fourth and fifth ferrite logical elements are connected according to the information bus.