KR100197411B1 - Circuit for generating acknowledge signal in switching system - Google Patents

Abstract

The present invention relates to an intra-device circuit for receiving a start signal from a processor and outputting the output timing of predetermined data as a recognition signal, comprising: a first combining unit for combining and outputting a start signal and a predetermined idle signal; A second combiner for combining and outputting an idle signal and a predetermined state-6 signal; And a shifter that sequentially shifts the output of the second combining unit and outputs the state-6 signal and the signal.

That is, the present invention has an effect of facilitating the reading of the device data of the processor by constituting the shifter using the D flip-flop and sequentially shifting the start signal for a required time to generate a recognition signal.

Description

A recognition signal generating circuit using shift of all electronic exchanges

FIG. 1 is a block diagram of a conventional electronic exchanger in which a processor reads and writes data to a memory in a device. FIG.

Figure 2 is a main part waveform diagram of the block diagram of Figure 1;

FIG. 3 is a circuit diagram of a recognition signal generating circuit using a shift of the entire electronic exchanger according to the present invention. FIG.

Fig. 4 is a main part waveform diagram of the recognition signal generating circuit using the shift of the electronic exchanger shown in Fig. 3; Fig.

DESCRIPTION OF THE REFERENCE NUMERALS

1: Processor 2: Device

3: memory 11, 13:

12: Shifter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating an acknowledgment signal (ACK) necessary for a processor to read information of a device in an electronic exchanger, and more particularly to a device for generating an acknowledgment signal (ACK) using a shifter. And a recognition signal generating circuit using a shift of an exchange.

In the operation of the electronic exchanger, the processors in the electronic exchanger perform a process of writing or reading data to / from external devices.

In the first figure, a block diagram is shown for the processor 1 to read and write the memory 3 data in the device 2. Here, the processor 1 is composed of the MC69030, and the bus is operated in a handshake asynchronous manner.

In this configuration, the processor 1 places the address signal on the address line SL as shown in FIG. 2, and the start address (START) of the memory 2 in the device 2 designates the address and notifies the start To the device (2).

The device 2 applies the enable signal ENABLE to the memory 3 in accordance with the start signal START and the memory 3 outputs the data by the enable signal ENABLE. At this time, the device 2 will be after 60 ns has elapsed.

On the other hand, the device 2 must notify the processor 1 that data is output, so that the processor 1 can know when to input data through the data line DL. Therefore, the device 2 is placed on the data line DL, and then the recognition signal ACK is applied to the processor 1 at the time T1 when the data is stabilized. By this recognition signal ACK, the processor 1 Is to read the data of the data line DL.

However, in the conventional method, there is no separate circuit for generating the acknowledgment signal (ACK), which causes many obstacles to use of the MC68060 processor.

An object of the present invention is to provide a recognition signal generating circuit using a shift of an electronic exchanger which generates a recognition signal (ACK) necessary for a processor to read data of a device .

A recognition signal generating circuit using a shift of an all-electronic exchanger according to the present invention relates to an intra-device circuit for receiving a start signal from a processor and outputting a predetermined data output time point as a recognition signal, A first combining unit for combining and outputting signals; And a shifter that sequentially shifts the output of the second combination unit and outputs the state-6 signal and the recognition signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3, a start signal START from the processor 1 is applied to the combiners 11 as shown in the recognition signal generating circuit diagram using the shift of the entire electronic exchanger according to the present invention. At this time, the combiners 11 apply the AND gate A1 and the OR gate OR1 as shown, and the OR gate OR1 performs logical addition of the output of the AND gate A1 and a state-6 signal . The output of the OR gate OR1 is inverted by the inverter I1 and applied to the shift circuit 10. [

As shown in the figure, the shift circuit 10 is configured such that a plurality of D flip-flops D1 to D6 are driven in synchronization with the clock signal CLK and simultaneously cleared by a clear signal (CLEAR) signal.

On the other hand, the D flip-flop D1 delays the signal of the inverter I1 for one clock (CLK) period, uses the signal of the inverted output terminal (Qbar) thereof as the idle signal IDLE, Is a signal that changes to a high level after a predetermined time elapses after input of a START signal as described later. Here, when the start signal START is in the logic low state as shown in FIG. 4, the AND gate A1 changes the output logic according to the idle signal IDLE. At this time, since the state-6 signal is also a signal applied in a logic high state after a predetermined time has elapsed since the start signal START is input, the OR gate OR1 changes its output logic in accordance with the output of the AND gate A1 .

The output of the OR gate OR1 is inverted by the inverter I1 and applied to the D flip flop D1 so that the D flip flop D1 outputs the terminal Q and the Q bar according to the idle signal IDLE. To change the output logic of. In the present invention, the output of the terminal (Q bar) of the D flip-flop D1 is used as the idle signal IDLE.

However, when the start signal START is input to the low level state, the AND gate A1 outputs the low level logic and the OR gate OR1 outputs the low level signal. That is, since the state-6 signal maintains the low-level logic state for a predetermined time after the start signal START of the low level is applied, the OR gate OR1 outputs the low level signal, and the inverter I1 outputs the low- The D flip-flop D1 applies a high-level logic to the output terminal Q and a low-level logic to the terminal Qb after a delay of one clock (CLK), since the output of the D flip-flop D1 is inverted and applied to the D flip- Level idle signal (IDLE).

The start signal START and the idle signal IDLE are applied to the combiner 13 and the combiner 13 is constituted by inverters I2 and I3 for inverting the output of the AND gate A2 as shown in Fig. .

Therefore, at the time when the start signal START and the idle signal IDLE are respectively at the low level state, the AND gate A2 outputs the logic of the high level, so that the D flip-flop D2 receives the start signal START , And outputs a high-level state-2 signal to the terminal Q after a delay of one clock (CLK). The D flip-flops D2-D6 are connected in series to the input / output terminals D and Q. The D flip-flops D3-D6 are connected to the D flip- State signal, the state-4 signal, the state-5 signal, and the state-6 signal, respectively, while shifting the clock signal CLK in synchronization with the clock CLK.

Here, as shown in FIG. 2, at the time when the recognition signal ACK is outputted, about four clocks are applied after the start signal (START) is inputted, and the device 2 outputs the recognition signal ACK At this point, the signal output from the D flip-flop D6 to the inverting terminal (Q-bar) at the time of outputting the state-6 signal can be used as the acknowledgment signal (ACK). At this time, the high-level state-6 signal is applied to the OR gate OR1 as described above, so that the D flip-flop D1 will output the high-level idle signal IDLE.

That is, the present invention has an effect of facilitating the reading of the device data of the processor by constituting the shifter using the D flip-flop and sequentially shifting the start signal for a required time to generate a recognition signal.

Claims (4)

An internal circuit of a device (2) for receiving a start signal (START) from a processor (1) and outputting an output time of predetermined data as a recognition signal (ACK) (13) for outputting a combined signal; A second combining unit 13 for outputting a combination of the idle signal IDLE and the predetermined state-6 signal and for outputting the idle signal IDLE according to the output of the first combining unit 11, And a shifter (12) which sequentially shifts the output of the one combination section (11) and outputs the state-6 signal and the recognition signal (ACK). 2. The semiconductor memory device according to claim 1, wherein the first combiner (11) comprises: an AND gate (A1) for logically multiplying the idle signal (IDLE) and the start signal (START) An OR gate (OR1) for outputting the state-6 signal and the output of the AND gate and outputting the result; And an inverter (I1) for inverting and outputting the output of the OR gate (OR1). 3. The recognition signal generating circuit according to claim 2, wherein the second combining unit (13) comprises a shift of the entire electronic exchanger constituted by an AND gate (A1) for ANDing and outputting the idle signal (IDLE) and the start signal. The semiconductor memory device according to claim 3, wherein the shifter (12) comprises: a D flip-flop (D1) for outputting the output of the first combining unit (11) in synchronization with a clock (CLK) to delay the idle signal (IDLE); D flip-flops (D2-D6) for sequentially outputting the outputs of the first combination unit 13 in synchronization with the clock (CLK) and delaying and outputting the acknowledge signal (ACK) And an electronic control unit for controlling the electronic control unit.