SU1361724A1 - Decoder - Google Patents

Description

The invention relates to automation and computing and can be used in the development of computing devices.

The purpose of the invention is to increase the speed of the decoder.

FIG. 1 is a diagram of a decoder j in FIG. 2; a time diagram with reference symbols.

FIG. 2 denote: 37–39 — the time pulse diagrams of the first, second, and third phases of the clock supply, respectively; 40-43 - time pulse diagrams, respectively, of signals on tires 17-20; 44-59 - time - pulse diagrams of signals, respectively, at the inputs and outputs of ternary elements 1-16. The point above (under) the x-axis on diagrams 44-59 corresponds to the recording of information on summing, to it the (subtracting) input of the ternary element, and the polarity of the output signal when reading from the ternary element is determined by the difference of points: if there are more points above the abscissa axis ( less) than under the axis of the abscissa, then a positive (negative) signal is read, if their

The decoder contains ternary elements 1-16, input buses 17-20 and output tires 21-36. Each ternary element performs ternary operations described in Table 1. These operations form a functionally complete system of logical functions and can be implemented on the basis of ferrite logic elements or on magnetic logical cells.

Table 1

The number is the same or not at all - there is no signal at the output. - The first, second and third summing (subtracting) inputs of the ternary element are equivalent to each other.

The decoder works as follows.

Code combinations in binary form are fed to the input buses 17-20 of the decoder (bus 17 with a weight of 2 °, bus 18 - 2% through bus 19 - 2, bus 20 - 2), while at one of the output tires 21 36, a positive polarity signal appears, uniquely corresponding to the input signal combination as shown in Table 2, (1 is a positive polarity signal, and O 3

signal of negative polarity or lack of signal), when applying a binary code to the bus 17-20 1

Input tire combinations

Weekend tire combinations

H

36 35 34 33 32 31 I 30 I 29128 27 26 25 24 23 122 21

20 19

17

2 3 45 6 7 8 9 10 000000000 001000000

About 1 About 1 1

ABOUT

one

ABOUT

ABOUT

one

about

0000 10000 00000100 101001000 1 10000000 1 1 1000000 000000000 001000000 0000000 1000000

about 1

one

one

1 10010000 1 1 1 100000

oh oh oh oh oh oh

010 oh oh oh oh

The decoder clock power supply system is three-phase, with the input signal combination on buses 17-20 through three phases (one clock cycle) of information transfer (FIG. 2). The second-phase clock pulse is read out from the ternary element 1-16. Signals are fed to buses 17-20 during the first-phase clock pulse.

The operation of the decoder in accordance with the input combination

is represented by a positive polarity signal, and O is a negative polarity signal.

table 2

10 0 0

about

0 0 0 0 0 0 0

11 12 13 14 15 16 17 18 19 20 0100000000 1000000000 0000000000 0000000000 0000000000 0000000000 о 0000 о о о о 1 0000000010

about

000000100

0000001000

about 0000 1

about

000

0100 o

000100000 001000000

about

000

about

000000000

o 0000 00 o o o

(0000) is as follows.

The clock pulse of the first phase of the first cycle according to the logic of the ternary element (Table 1) negative signal from the input bus 17 is transmitted to the first summing inputs of the ternary elements 1, 5 and 15, the first subtractive inputs of the ternary elements 2 and 4, the second subtractive inputs of the ternary elements 8 and 12 and the third subtractive input ternary ele5

6, the negative signal from the input bus 18 is transmitted to the first summing inputs of the ternary elements 8 and 12 and the first subtractive ternary elements 10, 14, 15 and 16, the negative signal from the input bus 19 is transmitted to the first summing inputs of the ternary elements 2 and 7, the first subtractive inputs of the ternary elements 5 and 12 and the second subtractive inputs of the ternary elements 13, 14, 15 and 16, the negative signal from the input bus 20 is transmitted to the third subtractive inputs of the ternary elements 7-14. The second-phase clock pulse is a positive signal-s ternary ale output 1-coagulant is transmitted to the output line 17, the image signal is uniquely corresponding input combination (0000).

Similarly, in accordance with FIG. G and 2, the conversion of the following x input combinations (Table 2).

Claims (1)

Formula iso p and e and The decoder containing the first - fourteenth ternary elements, the outputs of the seventh - fourteenth ternary elements are connected to the corresponding output buses, the first summing inputs of the first and fifth ternary elements, the first subtractive inputs of the second and fourth ternary elements are combined and connected to the first input bus, the first subtractive the inputs of the first and sixth ternary elements and the first summing inputs of the third and fourth ternary elements are combined, and connected to the second input bus, the first summing inputs The second and sixth ternary elements and the first subtractive inputs of the third and fifth ternary elements are combined and connected to the third input bus, the second subtractive inputs of the first to sixth threefold elements are combined and connected to the fourth input bus, the first summing inputs of the seventh, tenth, eleventh and the fourteenth ternary elements are combined with the first subtraction inputs 6 ten 20 25 the eighth, ninth, twelfth and thirteenth ternary elements, the first subtractive inputs of the seventh and tenth ternary elements are combined with the first summing inputs of the eighth and ninth ternary elements, the first subtractive inputs of the eleventh and fourteenth ternary elements are combined with the first summing inputs of the twelfth and thirteenth three elements, characterized in that, in order to improve the speed of the 15 VIY, the fifteenth and sixteenth ternary elements are introduced, the outputs of the first - sixth, n t the first and sixteenth ternary elements are connected to corresponding output buses, the first summing inputs of the fifteenth and sixteenth ternary elements are combined with the third subtractive inputs of the third and sixth logic elements, the first summed; the twelfth ternary elements and the first. subtractive input of the nine ninth ternary element and are connected to the first input bus, the first subtractive inputs of the fifteenth and the sixteenth ternary elements are combined with the first subtractive inputs of the seventh and eleventh ternary elements and the third subtractive inputs of the second and fifth ternary elements and connected to the second input bus; the second subtractive inputs of the fifteenth and sixteenth ternary elements are combined with the second subtractive inputs of the ninth, thirteenth and fourteenth ternary elements, with the first summing inputs of the seventh and eleventh ternary elements and the third subtracting inputs of the first and fourth ternary elements and are connected to the third input bus, the third subtractive inputs of the fifteenth and sixteenth ternary elements are combined with the third subtraction, and the inputs of the seventh to fourteenth ternary elements are connected to the fourth input busbar. thirty 35 40 45 50 Glakcto91 1st impulse  Record +1 record -1 jL counting 1 At the end of the meeting Editor E. Papp Compiled Oh, not bad Tehred And, Popovich Proofreader M. Maksimishinets Order 6304/57 Circulation 900 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4