SU1297225A1 - Analog-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to convert analog signals to digital code. The purpose of the invention is to increase the speed of the analog-to-digital conversion. A shortened coding cycle analog-to-digital converter contains a reference voltage generator 1, an input phase shifter 2, blocks 3 and 4 of phase comparators, encoders 5 and 6, number registers 7 and 8, a decoder 9, blocks 10 and 11 of the compensating current, key 12, displacement phase shifter 13, adaptation block 14 and. control unit 15. The introduction of the adaptation block 15 and the use of the forced compensation mode of the input analog signal made it possible to increase the speed of the analog-digital converter by fixing the compensation moment. 2 hp f-ly, 3 ill. O. cl

Description

11297225

The invention relates to measuring and computing techniques and can advantageously be used for analog-to-digital conversion.

The purpose of the invention is to demonstrate the speed of an analog-to-digital conversion.

Fig, 1 shows the structural diagram of the analog-to-digital converter; Fig 2 is a functional diagram of the control unit; Fig, 3 is a functional block diagram adaptation.

Analog-to-digital converter (FIG. 1) contains a reference voltage generator 1, an input phase shifter 2, blocks 3.4 of phase comparators, nifrators 5, 6, blocks 7.8 of the number registers, a decoder 9, blocks 10, 11 of the compensating current, a key 12, fa

H / 2 + ip /; H -f

lks / i; msxx xx i

THEN During the first conversion cycle, the signal With the phase shift H from the output of the phase shifter 2 is fed to the input of the coarse conversion stage. Depending on the value of H in block 3 it will work corresponding to 5

the number of phase comparators, after which, using the encoder 5, the numbers m of the binary bits of the output code are formed and entered in register 7. The recording of the conversion results into blocks 3, 5 and 7 is judged by the signals arriving respectively from the first, third and fifth outputs of control unit 15, From the output of register 7, the code of the most significant m bits goes to the output of the device and

displacement inverter 13, block 14 simultaneously to the input of the decoder 9.

station and control unit 15. The code from the output of the decoder 9 enters

to the information input of the adaptation block 14, on the second output of which a signal forms a m-signal including the block 10 of the compensation of the current, under the influence of which the phase of the output voltage of the phase shifter 2 decreases (shifts in the direction opposite to that in which it is transformed by the converted signal). Upon completion of compensation, the phase of the output voltage of unit 2 satisfies the condition

I The control unit (Fig. 2) contains inverters 16-20, I-NE elements 21-27, D-flip-flops 28-33, de-inflator FOR, pulse counter 35, pulse generator 36, delay elements 37, 38, 39 and driver 40 pulses

The adaptation block (FIG. 3) contains a GRUCPU 41 of (2 - 1) inverters, a group of 42 of - (1) AND-NOT elements, AND-NOT 43 - 47 elements, a decoder 48, a pulse generator 49, a pulse counter 50, D triggers 51, 52 and inverters 53, 54, 55,

The device (Fig, 1) works as follows.

After turning on the power by pressing the Start button, initial settings are made in the device blocks, Input 1, arriving at the information input of the phase shifter 2, is converted into a phase shift H of the harmonic voltage reference, which is fed to the input of the reference signal of the phase shifter 2 from the generator 1, thereafter It is not the input signal 1u that is subject, but the phase shift value unambiguously related to the value 1, the conversion of the value of H takes place in two cycles. In the first cycle, m higher bits of the code are formed, in the second cycle - (and - m) lower bits, Depending on the value of H, the following three modes of operation of the device are possible.

If the transformable quantity W satisfies the relation

thirty

35

  Hh la (7

hmaks x hmaks hmole

40

If the condition is met

.Kcl 3)

During the first conversion cycle, the signal from the third output of the adaptation unit turns on the compensating current block 11, under the influence of which the phase of the output voltage of the block 2 increases (shifts in the same direction as under the influence of the signal being converted) The termination of compensation ph 50 for the output voltage of the phase shifter 2 also satisfies relation (2).

If the transformable quantity H satisfies condition (2), then

55 senior bit of register 7 is written 1, and the remaining bits of this register are O. As a result, the first output of the adaptation block is for- 1-given a signal that opens the key

ABOUT

H / 2 + ip /; H -f

lks / i; msxx xx i

THEN During the first conversion cycle, the signal With a phase shift H from the output of the phase shifter 2 is fed to the input of the coarse conversion stage. Depending on the value of H in block 3, the corresponding 5

the number of phase comparators, after which, using the encoder 5, the numbers m of the binary bits of the output code are formed and entered in register 7. The recording of the conversion results into blocks 3, 5 and 7 is determined by the signals coming from the first, third and fifth outputs of the control unit 15, respectively. From the register 7 output, the code of the most significant m bits goes to the output of the device and

 simultaneously to the input of the decoder 9.

35

  Hh la (7

hmaks x hmaks hmole

If the condition is met

40

.Kcl 3)

During the first conversion cycle, the signal from the third output of the adaptation unit turns on the compensating current block 11, under the influence of which the phase of the output voltage of the block 2 increases (shifts in the same direction as under the influence of the signal being converted) The termination of compensation ph 50 for the output voltage of the phase shifter 2 also satisfies relation (2).

If the transformable quantity H satisfies condition (2), then

55 senior bit of register 7 is written 1, and the remaining bits of this register are O. As a result, the first output of the adaptation block is for- 1-given a signal that opens the key

12, which corresponds to the start of the second conversion cycle.

Thus, the second conversion cycle begins only when condition (2) is fulfilled. At the same time, the first information input of the block 4 phase comparators receives a voltage with a phase shift, satisfies the condition (2), and the second information input receives the voltage from the output of the phase shifter 13 bias. The displacement phase shifter provides a shift of the reference voltage by the value xmax corresponding to the beginning of the scale of the exact conversion stage. As a result, after opening the key 12 in block 4, a certain number of comparators are started, the code from the output of which is converted by the encoder 6 into the binary code (n-m) of the low-order bits and fed into the register 8j from the output of which the generated code is transmitted to the output of the device. The results of the conversion to blocks 4, 6, 8 are recorded by signals from the second, fourth and sixth outputs of block 15, respectively.

The signal from the first output of the block 14 | adaptation is also fed to the first input of the block 15 of the control and after opI .....

a certain delay sufficient to trigger the blocks 4, 6, 8 and 12 is output from the seventh output of block 15. This signal is used for initial settings in blocks 3-8, 14, after which the next conversion cycle of the input signal begins

The control unit (Fig. 2) works as follows.

After turning on the power, the Start signal, which arrives at the second input of the control unit, through the IS-NOT element 27 and the inverter 20 sets the D-flip-flop 33 to one state, the generator 36 starts, the pulses from whose output are counted by the counter 35. The decoder 34 extracts from the pulse sequence of the generator 3 is the second, quarter, sixth and eighth (with respect to the moment of starting the generator 36) pulses. The second pulse from the first output of the decoder 34 through the element AND-NOT 21 and the inverter 16 is fed to the first output of the control unit. Fourth pulse c. the second output of the decoder 34 through the element AND NOT 23 sets to one

state D-flip-flop 28, the signal from the output of which is fed to the third output of the control unit. The sixth pulse from the third output of the decoder 34 through the element IS-NOT 25 and the inverter 18 is supplied to the fifth output of the control unit. The eighth pulse from the fourth output of the decoder 34 causes the D-flip-flop 33 to zero, and through the delay element 39 zeroes the counter -1k 35. This completes the nepBbtfi control cycle, resulting in the device’s output of m high-order code bits and a signal from the output of adaptation block 14, one of the compensating current blocks (10, 11) is switched on.

Upon completion of the compensation process, the first input of the control unit receives a signal from the first output of the adaptation block 14, which sets the D-flip-flops 30, 31 and 32 to one state and through the pulse shaper 40, the elements 27, 20, 33 restart the generator 36 pulses. The second pulse from the first output of the decoder 34 through the element IS-NOT 22 and the inverter 17 is fed to the second output of the control unit, the fourth pulse from the second output of the decoder 34 through the element IS-NOT 24 sets

The D-flip-flop 29 is not in a state, the signal from the output of which goes to the fourth output of the control unit. The sixth pulse from the third output of the decoder 34 through the element IS-HE 26, the inverter 19 is fed to the sixth output of the control unit. The eighth pulse from the fourth output of the decoder 34 zeroes the D-flip-flop 33 and the counter 35. This completes the second cycle of operation of the control unit, as a result of which (n - m) low-order bits are generated at the device output.

A positive signal differential at the forward output of the D-flip-flop 32 (coinciding in time with the moment it arrives at the first input of the signal control unit) through the delay element 37 (the delay time of which exceeds eight periods of the pulse generator 36) zeroes the D-flip-flops 28–32 and enters the seventh output of the control unit. The pulse from the output of delay element 38 (time; the delay of which exceeds the delay time of element 37) is the signal for the start of the next conversion cycle.

Block adaptation (fig.Z) works as follows.

When the input signal I (input to the device) satisfies condition (1), at one information input from 2- (2-1) most significant bits of the adaptation block there is a signal at level 0. At the same time, at the output of the AND-NE element 46 and the second output of the adaptation unit appears level 1, which leads to the inclusion of the block 10 of the compensating current. At the same time, through the inverter 54, the AND-NOT element 47 D-flip-flop 52 is transferred to one state, the pulse generator 49 is started, the pulses from the output of which are counted by the counter 50. After a certain time, it is necessary to compensate for the input action I at the corresponding output of the decoder 48 level 1 appears, as a result, at one of the Lf - (- 1) outputs of group 42, out of (2 - 1 elements I-1S) level O appears, which through the element IS-HE 43 and the inverter 55 enters the clock D-flip-flop 51, which results in level 1 on the first output block adaptation. As a result, the device key 12 is opened and the lower bits of the device output code are formed. After a certain time, a pulse of the initial setup arrives at the input of the initial installation, which zeroes the counter 50 and the D-flip-flop 52, after which the next conversion cycle begins.

If the input signal I satisfies the condition) (3), then in this case the level 1 appears at the output of the NE-45 element and the third output of the adaptation unit, which leads to the switching on of the compensating current unit 11. The further process is similar to that described. When fulfilling inequality (2)

the level O appears on the (2 + 1) ohm bit of the information input of the block, and the compensating current blocks do not turn on. Signal with. (1) the bit of the information input of the adaptation unit arrives at the first input of the element AND-NE 44, which leads to the appearance at the first output of the adaptation unit of the signal opening the key 12,

whereby small bits are formed; the second bits of the output code.

Claims (3)

1. An analog-to-digital converter containing a control unit, a reference voltage generator, a coarse and accurate conversion stage, each of which is performed on series-connected phase comparator blocks, an encoder and a number register block, two compensating current blocks, whose outputs are connected ) 5, respectively, with the first and second inputs of the input phase shifter compensation, the first information input of which is an input bus, and the output is connected to the first information input of the phase comparators of the coarse conversion stage, the second information input of which is combined with the second information input of the phase shifter and with 25 by the input of the bias phase shifter and connected to the output of the reference voltage generator, the output of the phase shifter is connected to the first information input of the phase coherent unit of the exact conversion stage, the second information input of which is connected to the output of the key, the information input of which is connected to the input input phase shifter, outputs The 35 blocks of the coarse conversion number register are connected to the corresponding inputs of the decoder and are the output bus of the higher code bits, and the outputs of the number register The 40 exact steps are the output bus of the lower bits of the code, which is due to the fact that, in order to increase speed, an adaptation block was inserted into it, the information inputs of which are respectively connected to the outputs of the decoder, the first and second outputs are connected to the first control inputs, respectively, of the first and second blocks of the compensating current, and the third output is connected to the control input of the key and the first input of the control unit, the first and second outputs of which are connected to the control inputs of the blocks 55 phase comparators, respectively, of coarse and exact conversion steps, one third of G1 and the fourth outputs - with control of the encoder; 50 one accordingly, the fifth and sixth outputs, respectively, with the inputs of the recording of the number register blocks of the coarse and exact conversion stages, the seventh output, with the inputs of the initial installation of the adaptation unit, the phase comparators blocks and the number register units of both conversion stages, as well as with the second control inputs of the first and second blocks of the compensating current, the second input of the control unit is connected via a normally open button contact to the zero-potential bus. 2, The converter according to claim 1, wherein the control unit is implemented on six D-flip-flops, a decoder, a pulse counter, a pulse generator, seven IS-NOT elements, five inverters, three delay elements, a pulse shaper whose input is the first input of the control unit, and the output is connected to the first input of the first NAND element, the output of which through the first inverter is connected to the setup input of the first D-flip-flop, the information and clock inputs of which are connected to the ground potential of zero, direct output It is connected to the trigger input of the pulse generator, the output of which is connected to the counting input of the pulse counter, the outputs of which are connected respectively to the inputs of the decoder, the first output of the depuser is connected to the first inputs of the second and third elements AND-NOT, the outputs of which are connected to the inputs of the second and third inverters respectively The outputs of which are respectively the first and second outputs of the control unit, the second output of the decoder is connected to the first inputs of the fourth and fifth elements AND-NOT, the outputs of which are connected to The setting inputs of the second and third D-flip-flops respectively, the information and clock inputs of which are connected to the zero potential bus, and the outputs are the third and fourth outputs of the control unit, the third output of the decoder is connected to the first inputs of the sixth and seventh AND-NES elements, the outputs of which connected to the inputs of the fourth and fifth inverters, respectively; TopF.rx are respectively the fifth and sixth outputs of the control unit, the fourth output of the decoder is connected to the zero input of the first D-flip-flop and through the first delay element - with the zero input of the pulse counter, the clock inputs of the fourth, fifth and sixth D-flip-flops are combined with the input pulse generator, the setup inputs of the fourth, fifth, and sixth D-flip-flops are connected to the power bus, the direct outputs of the fourth, fifth, and sixth D-flip-flops are connected to the second inputs of the corresponding but third, nth and seventh ele I-NOT, the information inputs of the fourth, fifth, and sixth D-flip-flops are combined with their inverse outputs and connected to the second inputs of the second, fourth, and sixth AND-H, respectively, the direct output of the sixth D-grigger is connected to the inputs of the second and third the delay elements, the output of the last of which is connected to the zeroing inputs of the second, third, fourth, fifth, and sixth D-flip-flops, is the seventh output of the control unit; the output of the second delay element is connected to the second input of the first AND-NOT element, mp Tille input of which is the second input of the control unit. 3. The converter according to claim 1, characterized in that the adaptation unit is made on a group of (1) inverters, where m is the number of bits of the output code of the device, a group of (1) AND-NOT elements, five AND- elements NOT, two D-triggers, three inverters, a pulse generator, a decoder, with a pulse maker, whose outputs are respectively connected to the inputs of the decoder, and the counting input is connected to the output of the pulse generator, the trigger input of which is connected to the forward output of the first D-flip-flop, inverse output and 1 formatting input of which The installation input is connected to the power bus, and the clock input is connected to the output of the first NAND element, whose inputs are connected via the first and second inverters to the output of the second and third AND NAND elements, respectively, and are the third and second outputs of the adaptation unit, in :: odov group from. (1) Inverters, respectively, are combined with the inputs of the second NAND element and are informational.  the inputs of the lower bits of the adaptation block, the inputs (1) of the group of (1) inverters are respectively combined with the inputs of the third AND-NOT element and are the information inputs of (- 1) the higher bits of the adaptation block, the outputs of the group of (1) inverters respectively connected with the first inputs of a group of (1) elements AND-NOT, the second inputs of which respectively are connected to the outputs of the decoder, and the outputs are connected to the inputs of the fourth AND-HF element, the output of which is connected through the third inverter to the first input of the fifth AND-PE element, the second input of which is an information input (2 - - 1) of the block adaptation, and the output is connected to the clock input of the second D-trigger, whose information input and inverse output are combined, the setup input is connected to the power bus, and the forward output is the first output of the adaptation block, the zeroing inputs of the first, second D-triggers and pulse counter are combined and are the input of the initial installation unit adaptation. , ii X. i 23 Fe / g. Z :: $ N fig.Z Compiled by H. Kapitanov Editor n. Shvyschka Tehred A. Kravchuk Proofreader N. Korol Order 795/61 Circulation 902 Subscription VNIITSH USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Proizvodstvenno-polygraphic enterprise, Uzhgorod, Projecto st., 4 Bx.J {if.O}